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AssigneeNumerical Technologies, Inc.
InventorsMichel Luc Cote, Philippe Hurat, Christophe Pierrat
Estimating the term…
One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the specification that no not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.
A method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising:
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising:
An apparatus for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising:
A mask to be used in an optical lithography process, wherein the mask is created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising:
An integrated circuit created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Term end not estimated
Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles…
Circuit design: circuit design at the physical level
Details relating to the type or aim of the analysis or the optimisation: manufacturability analysis or optimisation for manufacturability
Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation: total factory control, e.g. smart factories,…
Backward citations are indexed for grants only.
1. Field of the Invention
The invention relates to the process of designing an integrated circuit. More specifically, the invention relates to a method and an apparatus for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size.
2. Related Art
The file of this patent contains at least one drawing executed in color. Copies of this patent with color drawing(s) will be provided by the Patent and Trademark Office upon request and payment of the necessary fee.
FIG. 1 illustrates how the manufacturing process is simulated in accordance with an embodiment of the invention.
FIG. 2 is a flow chart illustrating the wafer fabrication process in accordance with an embodiment of the invention.
Wafer Fabrication Process
FIG. 2 is a flow chart illustrating the wafer fabrication process in accordance with an embodiment of the invention. The system starts by applying a photoresist layer to the top surface of a wafer (step 202). Next, the system bakes the photoresist layer (step 204). The system then positions a mask over the photoresist layer (step 206), and exposes the photoresist layer through the mask (step 208). Next, the system optionally bakes the wafer again (step 214) before developing the photoresist layer (step 216). Next, either a chemical etching or ion implantation step takes place (step 218) before the photoresist layer is removed (step 220). (Note that in the case of a lift-off process, a deposition can take place.) Finally, a new layer of material can be added and the process can be repeated for the new layer (step 222).
Design and Manufacturing Process