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US 2003/0192012 A1Published application
System and method to determine impact of line end shortening
AssigneeNumerical Technologies, Inc.
InventorHua-Yu Liu
Life of this patent
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AssigneeNumerical Technologies, Inc.
InventorHua-Yu Liu
Estimating the term…
A critical dimension, or width, of a feature, or a semiconductor device, can be measured to provide direct and meaningful information regarding the impact of line end shortening, or length, on the function of the device. Specifically, a location on the feature where the width will have an impact on device performance can be selected. Using a simulation, the width at that location can be computed. Given the difficulties of direct measurement of line end shortening and the relationship between the width measurement and the impact on device performance, better layout checking is facilitated than by standard measurements of line end shortening.
A method of determining an impact of line end shortening in a layout, the method comprising:
An integrated circuit including;
A system for determining an impact of line end shortening for a gate, the system comprising:
A computer program product comprising:
A simulation report regarding one or more features on a layout, at least one feature being a line, the simulation report comprising:
A simulation report regarding a layout, the simulation report comprising:
A method of determining an impact of line end shortening on a feature, the method comprising:
A mask for fabricating an integrated circuit, the mask comprising:
Dependencies are inferred from the claim text.
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Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
Computing and data processing
Term end not estimated
1. Field of the Invention
The invention relates to analyzing printed image distortion, and in particular to a system and method of determining the impact of line end shortening in the production of integrated circuits.
2. Description of the Related Art
FIG. 1A illustrates a transistor formed by a gate and two diffusion areas.
FIG. 1B illustrates the effect of line end shortening on the gate shown in FIG. 1A.
FIG. 1C illustrates the effect of line end shortening if the endcap margin is too small.
In accordance with one feature of the invention, a critical dimension of the feature can be measured to determine the impact of line end shortening. The critical dimension measurement advantageously provides accurate and meaningful information regarding device performance irrespective of endcap margin.
FIG. 3A illustrates one exemplary methodology 390 for obtaining this critical dimension. In step 391, a model can be constructed. The model can be developed based on the equipment, equipment settings, and other parameters used in the fabrication process. The model can be built by performing the fabrication process one or multiple times with test patterns, observing the actual features printed using these test patterns, and fitting a set of equations or matrix transformations that most nearly reproduce the locations of edges of features actually printed as output when the test pattern is provided as input. In one embodiment, the ModelGen™ and/or ModelCal™ tools from Numerical Technologies, Inc. of San Jose, Calif., can be used to create suitable models.
A model uses computational resources in proportion to the number of evaluation points where layout analysis is performed, e.g. approximately O(n) in the number of evaluation points. Specifically, to provide time efficient yet accurate results, the model can be run at selected points, i.e. the evaluation points, located on the edges of features, to determine the correction needed, if any, at each evaluation point to more closely approximate the desired design.