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AssigneeGalazar Networks, Inc.
InventorsMatthew Coakeley, Erik Trounce, David Kirk, Michael Vandegriend, Richard DeBoer, Nizar Rida
Estimating the term…
Systems and methods for encoding and decoding serial bit streams are provided. A parity bit is computed for each nibble, with the parity alternating between odd and even in a regular manner for normal data, and with parity having predetermined different patterns to indicate the start of a packet or the end of a packet. Special code words indicate the idle state and an error state. In some systems an extra vertical parity channel is provided in association with a group of data channels, the vertical parity channel effectively providing a protection channel.
A method of encoding an input bit stream to produce a serial encoded output comprising:
A method of encoding an input bit stream to produce an encoded output comprising:
An encoder for encoding a serial bit stream to produce an encoded output the encoder comprising:
A method of decoding a received serial bit stream comprising:
Dependencies are inferred from the claim text.
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Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit: using single parity bit
Coding
Term end not estimated
The invention relates to systems and methods of performing serial encoding and decoding for data and control interfaces.
High speed serial communications paths, such as may exist between components in an optical networking node, are typically subject to very low error rates. An example of a baseline bit error rate which might be desirable for such serial links is 10−12. An example rate of such a link is 2.5 Gbps for a short haul connection between a port card and a switching matrix. In such a system, when operating normally, it takes an average of thousands of seconds before an error will occur. Various coding schemes have been developed for such applications.
One scheme not originally designed for this application but which has become a popular choice is commonly referred to as 8B/10B is taught in U.S. Pat. No. 4,486,739 to Franaszek, et al. entitled “Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code” which issued Dec. 4, 1984. With this scheme, 8 bit bytes are encoded into 10 bit code words. The code is crafted to allow a maximum of 4 “1”s or 4 “0”s in a row for data words. This is because another purpose of such codes is to provide sufficient transitions that timing recovery can be performed at a decoder, typically at a receiver. There are special start of packet (SOP) and end of packet (EOP) sequences which indicate the start of a new packet and the end of a current packet respectively. These SOP and EOP packets introduce overhead since data does not start until after the SOP.
Preferred embodiments of the invention will now be described with reference to the attached drawings in which:
FIG. 1 is a block diagram of an encoder provided by an embodiment of the invention;
FIG. 2 shows a set of coded data sequences coded using the encoder of FIG. 1 and also employing certain special code words;
Referring first to FIG. 1, shown is a block diagram of a high speed encoder provided by an embodiment of the invention. The high speed encoder has a raw input 10 typically consisting of uncoded bits. However, these “uncoded bits” may be bits to which some other coding has already been applied independent of the processing applied by the encoder of FIG. 1. In a preferred embodiment, the high speed encoder processes the bits eight bits at a time. The raw input 10 is connected to a scrambler 12 which produces a scrambled input 14 which is connected to a parity calculator 16. The parity calculator 16 produces a serial coded output 22 as a function of the scrambled input 14, a FDSD (first data stream delineation) input 18 and in some embodiments also a SDSD (second data stream delineation) input 20.
In some embodiments, the raw input 10 is a packetized serial data stream. In such embodiments, the FDSD input 18 consists of a start of packet indication for each packet and the SDSD input 20 consists of an end of packet indication for each packet. It may not be necessary to include SDSD input 20 for packetized serial data streams which include packet length specified in packet headers.
In some embodiments, the raw input 10 is a multi-framed and framed serial data stream consisting of fixed length multi-frames, with each multi-frame containing a fixed number of frames and each frame containing a number of slots. If there is no data to transmit during a given slot, then an idle code word is transmitted. In such embodiments, the FDSD input 18 is used to indicate the start of a multi-frame, and the SDSD input 20 is used to indicate the start of each frame.