Built-in self test circuit

#(a) Field of the Invention

#The present invention relates to a built-in self test (BIST) circuit, and more particularly, to a BIST circuit which is capable of generating a test pattern including series of test input signals and test result signals.

#(b) Description of the Related Art

#FIG. 1 is a block diagram of an LSI including a BIST circuit according to a first embodiment of the present invention.

#FIG. 2 is a block diagram of the BIST circuit shown in FIG. 1.

#FIGS. 3A to 3C are schematic diagrams of data stored in th4e memory cells during a marching pattern test.

#The BIST circuit according to the present invention is preferably incorporated in an LSI including a logic circuit and/or memory device, such as system LSI, logic LSI and DRAM.

#If the BIST circuit according to the present invention is incorporated in a logic LSI or logic core block, for example, another BIST circuit is preferably incorporated therein including a test pattern generator which generates a scan-in test pattern and a scan-out data expected pattern for conducting a scan path test. The scan path test is generally used for examining the presence or absence of a physical defect in the LSI during a product test. The physical defect may arise due to an incomplete fabrication step such as in a diffusion step or etching step in the fabrication process of the LSI. For detecting the physical defect, the verification test pattern may be used in the product test while assisting the scan path test.

#The design verification test pattern is preferably described in a behavior level language for allowing a defect to be found in the early stage of the design of the LSI.