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AssigneeMicron Technology, Inc.
InventorsWarren M. Farnworth, James M. Wark, Eric S. Nelson, Kevin G. Duesman
Estimating the term…
An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. A method for performing such testing once the test mode has been initiated and for repairing any failing elements found during testing includes providing test signals to the dice, receiving response signals from the dice, evaluating the response signals to identify any failing elements in the dice, programming the failing elements' addresses into anti-fuses in the dice with a programming voltage, confirming that the addresses are programmed by determining the resistance of the anti-fuses, re-testing the dice, receiving response signals from the re-tested dice, and evaluating the response signals to confirm all repairs.
A switching apparatus for switching first and second voltages to a function circuit in at least one integrated circuit die having at least one external communication terminal, the at least one integrated circuit die being provided in a module having a module terminal for receiving the first voltage from circuitry external to the module, the switching apparatus comprising:
An integrated circuit die comprising:
An integrated circuit module comprising:
A method for initiating at least a first mode and at least a second mode in a function circuit in each circuit die of one or more integrated circuit dice in an integrated circuit module having a module terminal, the function circuit being of the type to enter the first mode and the second mode in response to receiving respective a first mode initiate signal and a second mode initiate signal, each integrated circuit die including one or more bond pads connected to circuits for receiving the test mode initiate signal at the module terminal, the method comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Using programmable devices: with redundancy programming schemes
Testing of digital circuits: arrangements for setting the Unit Under Test [UUT] in a test mode
Test of Modular systems, e.g. Wafers, MCM's: test of Multi-Chip-Moduls
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: comprising I/O circuitry
Term end not estimated
1. Technical Field
This invention relates in general to integrated circuit (IC) dice and, in particular, to devices and methods for testing dice in IC modules.
2. State of the Art
FIG. 1 is an isometric view of a conventional integrated circuit module;
FIG. 2 is an isometric, block and schematic view of an integrated circuit module including a switching circuit and an impedance circuit in accordance with this invention;
FIGS. 3A-C are schematic views of alternative versions of the switching circuit of FIG. 2;
As shown in FIG. 2, an inventive integrated circuit (IC) module 20 includes IC dice 22 having function circuits, such as input buffers 24, selectively receiving a test mode initiate signal, such as a supply voltage Vcc, through a module terminal 26, a switching circuit 28, and test mode enable bond pads 30 (e.g., Output Enable (OE) bond pads). It will be understood by those having skill in the field of this invention that the IC module 20 may be any electronic structure having at least one die accessed externally through terminals, including, for example, any Multi-Chip Module (MCM), such as a Single In-line Memory Module (SIMM), a Dual In-line Memory Module (DIMM), a Random Access Memory (RAM) card, a flash Read-Only-Memory (ROM) module or card, a Synchronous Dynamic RAM (SDRAM) module or card, and a Rambus RAM module or card. It will also be understood that the dice 22 may be any dice for purposes of this invention, including, for example, DRAM dice, Static Random Access Memory (SRAM) dice, Synchronous Graphics Random Access Memory (SGRAM) dice, ROM dice, and processor dice.
Also, it will be understood that the function circuits may be any circuitry on a die for initiating a test mode in the die, the test mode initiate signal may be any signal for initiating a test mode in a die, the module terminal 26 may be any terminal including, for example, an MCM pin (e.g., a SIMM, DIMM, RAM card, RAM module, ROM card, or ROM module pin), the switching circuit 28 may be, for example, a fuse or a transistor or any other device for selectively isolating the function circuits from the module terminal 26, and the test mode enable bond pads 30 may be any bond pads connectable to a function circuit for enabling a test mode in a die. Further, it should be understood that although the switching circuit 28 is shown in FIG. 2 as being a single circuit coupled to the module terminal 26, it may instead comprise a plurality of circuits, each one coupled to the module terminal 26 and one of the dice 22.
In response to receiving the test mode initiate signal, the input buffers 24 initiate a test mode in the dice 22. In this mode, various test signals may be provided to the dice 22 in a well known manner to test the circuitry thereon, and the dice 22 then output various response signals indicating the presence of any failing circuitry. While the test mode initiate signal, such as the supply voltage VCC, is being provided to the test mode enable bond pads 30 and the input buffers 24, an impedance circuit 32, such as, for example, a resistor, resistance-connected MOS transistor, or anti-fuse, supports a difference in voltages between the test mode initiate signal at the test mode enable bond pads 30 and an operational mode enable signal, such as a reference voltage VSS, at a reference terminal 34, such as, for example, an MCM pin (e.g., a SIMM, DIMM, RAM card, RAM module, ROM card, or ROM module pin). It will be understood that although the impedance circuit 32 is shown in FIG. 2 as being a single circuit coupled to the reference terminal 34, it may instead comprise a plurality of circuits, each one coupled to the reference terminal 34 and one of the dice 22.