Scheduling the concurrent testing of multiple cores embedded in an integrated circuit

#The present invention relates generally to testing integrated circuits, and more specifically to a method for scheduling the testing of multiple cores embedded in an integrated circuit or system-on-chip.

#Many of today's integrated circuit (IC) designs consist of a complete system on a chip (SOC). An SOC integrates multiple pre-designed and reusable circuits, termed “cores,” onto a single integrated circuit. This integration allows SOC manufacturers to reduce design time and lower production costs. A basic SOC 10 containing multiple embedded cores is shown schematically in FIG. 1. Multiple cores 14 are embedded in the SOC 10. The cores 14 may comprise processor cores, memory cores, or logic cores. Each core has a number of core terminals or pins 16 that provide access to the internal circuitry of the core. Similarly, the SOC 10 has a number of integrated circuit or SOC terminals or pins 12 that provide access to the internal circuitry of the SOC and the multiple cores.

#The time required to effectively test an SOC, which requires the separate testing of each individual core, is a major factor in overall production time. Therefore, as SOCs are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee high fault coverage while minimizing test costs and chip area overhead are essential.

#FIG. 1 is a plan view schematically showing a basic SOC containing multiple embedded cores.

#FIG. 2 is an illustration schematically showing a two-dimensional rectangle representing a test of a core.

#FIG. 3 is an illustration schematically showing a two-dimensional bin representing an SOC test schedule.

#The methods for scheduling the concurrent testing of embedded cores as shown and described herein are implemented in software stored on a computer-readable medium and executed on a general-purpose computer. The disclosed method, for example, can be implemented in computer-aided testing tools. Further, the disclosed method may be executed on a single computer or on a networked computer. For clarity, only those aspects of the software germane to the disclosed technology are described; product details well known in the art are omitted. For the same reason, the computer hardware is not described in further detail. It should thus be understood that the disclosed technology is not limited to any specific computer language, program, or computer.

#The invention is described below in connection with representative embodiments that are not intended to be limiting in any way. Although the specific embodiments are discussed as relating to an SOC, the method described can be applied to any integrated circuit containing multiple embedded cores. Additionally, although the specific embodiments discussed below focus on cores tested using externally generated test patterns, the method described can be applied to the testing of cores using internally generated test patterns (e.g., cores using Built-In-Self-Test (BIST) technology).

#General Considerations