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US 2003/0191995 A1Published application
System for communicating with synchronous device
AssigneeNone recorded
InventorsIgor Anatolievich Abrosimov, Alexander Roger Deas
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AssigneeNone recorded
InventorsIgor Anatolievich Abrosimov, Alexander Roger Deas
Estimating the term…
The present invention relates to systems for communicating with synchronous devices, in particular, to automatic test equipment (ATE) for memory device testing and, more specifically, to a test system for testing a high-speed synchronous memory device using DQS signals obtained from the memory device to achieve the precise fault strobe timing characteristics. The test system for testing a memory device comprises a synchronisation unit for triggering fault strobe generators with respect to DQS signals from the memory device under test. The invention is particularly appropriate for testing memory devices having reference signal for data receiver synchronisation, such as DDR Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR SGRAM (Synchronous Graphics Random Access Memory), DDR II SDRAM, QDR SRAM, etc.
A test system for testing a synchronous memory device having a data strobe generating means for generating at least one data strobe signal, the test system comprising:
A method of testing semiconductor devices including:
A system for communicating with a synchronous device having a data strobe generating means for generating a data strobe signal, the system comprising:
Dependencies are inferred from the claim text.
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Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: external testing equipment for…
Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing: arrangements in static stores specially…
Using transistors: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
Static stores
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This application is a continuation-in-part application of PCT/RU01/00486 filed on Nov. 5, 2001, claiming priority from GB application 0026849.0 filed on Nov. 3, 2000, all of which are incorporated herein by reference.
The present invention relates to systems for communicating with synchronous devices, in particular, to automatic test equipment (ATE) for memory device testing and, more specifically, to a test system for testing a high-speed synchronous memory device, and a method of testing thereof.
Test systems used for testing memory devices should be able to test new memory devices at their maximum speeds. A test system generates test patterns, feeds them to the memory device under test and compares the data read from the memory device under test with what is expected, but the timing of the strobe and its relation to the address, data and control signals is a critical parameter: that is, it is subject to a very tight timing tolerance in high speed systems.
For a better understanding of the present invention and the advantages thereof and to show how the same may be carried into effect, reference will now be made, by way of example, to the following description with reference to the accompanying drawings in which:
FIG. 1 is a diagram showing the data valid window and timing of a read cycle for SDR SDRAM;
FIG. 2 is a diagram showing the data valid window of an 8-bit DDR SDRAM;
In FIG. 4, an example embodiment of the memory test system in accordance with the proposed invention is presented.
The system is intended for testing a synchronous memory device under test 4, e.g. a DDR SDRAM type. As mentioned earlier, this memory device is of a type that has a data strobe generating means for generating at least one data strobe signal or, in other words, DQS signal.
A test pattern generator 11 provides an appropriate sequence of test signals including address, data, control and clock signals. The test pattern generator can be provided, if necessary, with a suitable SDR (single data rate) to DDR (double data rate) converters.