Semiconductor device for memory test with changing address information

#1. Field of the Invention

#The present invention relates to a semiconductor device for memory test with changing address information provided with an address decoder and an internal memory having a function for producing the data of a memory array region by the address decoder and, in particular, to a semiconductor device for memory test with changing address information in which the memory array region of one internal memory is divided into independent regions that do not affect each other and in which the self-test of the internal memory itself is conducted.

#2. Description of the Related Art

#FIG. 1 is a block diagram to show the configuration of a semiconductor device for memory test with changing address information in accordance with the preferred embodiment 1 of the present invention along with a tester.

#FIG. 2 is a diagram to describe one example of an address converting circuit shown in FIG. 1.

#FIG. 3 is a block diagram to show one example of an address interchanging circuit shown in FIG. 1.

#The preferred embodiments of the present invention will be hereinafter described.

#Preferred Embodiment 1

#FIG. 1 is a block diagram to show the configuration of a semiconductor device in accordance with the present invention of the present invention along with a tester. In FIG. 1, a reference character 21 denotes a semiconductor device; a reference character 22 denotes a CPU; a reference character 23 denotes an address converting circuit (address converting means); and a reference character 24 denotes an internal memory that is a semiconductor memory device. The CPU 22 is connected to an internal address bus 22a and an internal data bus 22b. The internal memory 24 is connected to the internal data bus 22b and, via the address converting circuit 23, the internal address bus 22a. Here, the internal memory 24 has a memory array 24a, an address decoder (decoder) 24b, and a sense amplifier 24c. The memory array 24a is divided into a memory region to be tested (data region: the second region) 31 and a test program region 32. The address converting circuit 23, as will be described later, selects the memory region to be tested 31 or the test program region 32 in accordance with a control signal for a test C[n] (where n is an integer not smaller than 1).