Method of generating a test suite

#The invention relates to a method and apparatus for generating a test suite of instructions for testing the operation of a processor.

#During the development and manufacture of a processor it is necessary to test the processor for correct operation in as many different situations as possible. It is therefore necessary to generate a sequence of instructions, known as a regression test suite, to test the operation of the processor.

#Modern processors frequently use pipelines to increase the speed of operation. In a pipeline mode of operation, a sequence of instructions is processed through a pipeline, in such a manner that while the processing of one or more instructions is being carried out the processor starts to process the next instruction or instructions simultaneously. For example, instructions may pass through a pipeline of steps, including instruction cache read, instruction decode, instruction execution and writeback, in such a manner that later instructions are being read and decoded while earlier instructions are still being executed and the results written back. Pipeline processors increase the need for testing, since it is necessary to test whether the processor can block or otherwise fail when presented with various sequences of instructions.

#A specific embodiment of the invention will now be described, purely by way of example, with reference to the accompanying drawings, in which:

#FIG. 1 is a schematic diagram of part of a fuzzy state machine;

#FIG. 2 is a flow diagram of a method according to the invention; and

#The invention is based on a fuzzy finite machine with a number of states and a set of weights for random decisions for each state. Both the random decisions and the weights may be different for each state. One of the random decisions for each state is the decision of which state to choose next.

#FIG. 1 illustrates part of a fuzzy finite state machine for use in an instruction stream generator. In this arrangement, each state corresponds to a single instruction. When generating an instruction, it is in general not sufficient to generate the instruction (also known as the opcode). Other properties associated with the instruction need to be generated, including the operands, for example which addresses the instruction is to access, and which register it is to use. The other random decision associated with each state is the decision as to the next state, which again is selected using weights.

#Referring to FIG. 1, an illustrated schematic part of a state machine includes a number of states 2 and transitions between the states 4. It should be noted that some of the transitions between states are self transitions 6 wherein the next state is the same state. This allows the generation of sequences of like instructions. Consider state 8 which relates to a conditional branch instruction. The state 8 includes a first set of weights 10 (W1, W2, . . . W4) relating to the probabilities that the next state is one of a number of subsequent states 12 or a self transition along path 6 back to the original state 8. Other random decisions for the conditional branch instructions represented by the state 8 may include, in this example, the choice of which internal register is to be tested for the conditional branch. In the example register 1 (R1) has a weight (W5) and register 2 (R2) a weight (W6). Further weights W7 to W10 reflect the probabilities of different options as to where the conditional branch jumps to.