Clock signal generating circuit

#The present invention generally relates to a clock signal generating circuit for a computing device, and more particularly, the present invention relates to a clock signal generating circuit for generating a ramped clock signal.

#Conventional computing systems utilize a clock signal generating circuit to provide timing information to a plurality of flip-flops. The flip-flops store binary states, such as 1's and 0's contingent on the absence or presence of a voltage or charge in the flip-flop. The binary states, read or written in the flip-flops, are then used for combinational boolean logic for operation and calculation procedures in the computing system. When writing a logic state in the flip flop by a device external to the flip flop is desired, an oscillating voltage or clock signal operates the flip fop to cause a voltage value representative of the stored state to be stored to be written to the latching circuit in the flip-flop, latch the voltage value and hold it available for reading devices external to the flip-flop. The clock signal is commonly a square wave that drives a gate of a transistor of the flip-flop. The clock signal generating circuit, external to the flip-flops, generates the signal to effectuate read, write and timing processes in the computing device. The square or abrupt signal drives the gates of transistors in the flip-flop to turn them ON and OFF in a relatively quick manner.

#While this structure effectively allows a computing system to effectuate reading of stored logic states contained within the flip-flops, drawback exists. Specifically, only a portion of a computing system's flip-flops are actually read during any given read request. The remainder, however, still receive the clock signal. Commonly, the energy of the clock signal driving the unread flip-flops is dissipated therein, thereby creating energy inefficiencies and increased heat dissipation. When this dissipation effect is multiplied with the numerous flip-flops contained within a computing device, the overall efficiency of that computing device is compromised. The present invention was developed in light of these and other drawbacks.

#The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

#FIG. 1 is a schematic view of a memory storage circuit according to an embodiment of the invention;

#FIG. 2 is a schematic view of a memory storage circuit and clock generator according to an embodiment of the invention;

#It is to be understood that the present invention may be embodied in other specific forms without departing from its essential characteristics. The illustrated and described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

#Referring now to FIG. 1, the present invention is shown and described. In FIG. 1, a flip-flop 10 includes clock signal receiving circuit 12, input value 14, reading element 16, and latching element 18. In an embodiment of the invention, clock signal receiving circuit 12 includes two cross-coupled PMOS transistors 20a and 20b. Input value 14 includes a binary value 22, which by absence or presence of a voltage “1” or “0” indicates a Boolean state. Inverter 24b provides an inverted version of binary value 22 to opposite sides of flip-flop 10. An additional inverter can also be added between the inverter 24b and the binary value 22 to, again, invert the binary value supplied to opposite sides of flip-flop 10.

#Reading element 16 includes NMOS transistors 26a and 26b that cooperate with input value 14 and inverter 24b to allow binary value 22 to be read in response to a clock signal. Finally, latching element 18 includes cross-coupled NOR gates 28A and 28B to latch binary value 22 and allow it to be read by an external device.