US 2003/0191974 A1 · Control method of semiconductor memory device and semiconductor memory device

Abstract

It is intended to provide a control method of a semiconductor memory device and a semiconductor memory device capable of shortening pre-charge operation time that comes after termination of successive data access operation, namely, successive data read/write operation, without causing deterioration of restore voltage to memory cells and delay of initial data access time. An activated word line WL0 is deactivated with appropriate timing that is between time after bit line pairs (BL0 and /BL0, . . . BLN and /BLN) are differentially amplified up to full amplitude voltage level and time where column selecting lines CL0, . . . CLN are selected. That is, deactivation time τA for the word line can be embedded in a period of successive data access operation. Pre-charge operation can be terminated within time that is a sum of deactivation time τAB of a sense amplifier and equalizing time τC of the bit line pairs. Thereby, pre-charge period can be shortened.

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Drawings

Claims25

Dependent claims

A control method of a semiconductor memory device for executing successive access operation, the control method comprising:

data amplification step where a word line is activated and a plurality of memory cells are connected to a plurality of bit lines to amplify data;
and
column selection step where a column connects at least one bit line out of the plurality of the bit lines and at least one data line in order after the data amplification step;
word line deactivation step where a word line is deactivated in a period that satisfies following two conditions (1) and (2):
(1) a period after predetermined timing taken after the data amplification at the plurality of bit lines completes;
and (2) non-column selection period between completion of an anterior first column selection and start of a posterior second column selection.

3 more elements

A control method of a semiconductor device comprising:

word line activation step where a word line is activated in accordance with start request of successive access operation so as to connect a plurality of memory cells to a plurality of bit lines, respectively;
data-amplification step where a plurality of data read out to the plurality of bit lines from the plurality of memory cells are amplified;
data-access-start step where the successive access operation is started by conducting column selection for connecting at least any one of the plurality of bit lines to at least one data line after amplification level in the data-amplification step reaches predetermined level;
word line deactivation step where the word line is deactivated after the amplification operation in the data-amplification step is completed and while the column selection in the data-access-start step is deactivated;
data-access-keep step where the column selection is conducted in order with respect to any one of the plurality of bit lines so as to keep the successive access operation after the word line deactivation step;
and
pre-charge step for initializing the plurality of bit lines by stopping data amplification operation in accordance with termination request of the successive access operation.

4 more elements

A semiconductor memory device comprising:

a plurality of bit lines each of which is connected to each of a plurality of memory cells when a word line is activated;
a plurality of column selecting sections where each of the plurality of bit lines is individually selected;
and
at least one data line to be connected to at least any one of the plurality of bit lines through at least any one of the plurality of column selecting sections;
the semiconductor memory device conducting successive access operation by selecting at least any one of the plurality of column selecting sections in order, wherein the semiconductor memory device further comprises:
a first-column-selection-termination detector circuit that detects termination of selecting a first column selecting section to be selected in advance;
a timing informer section that informs a period that is after completion of data amplification and from termination of selecting the first column selecting section to be selected in advance until start of selecting a second column selecting section to be selected after selection of the first column selecting section;
and
a word line deactivating circuit that becomes active when none of the plurality of column selecting sections operates is selected in accordance with an informing signal from the timing informer section.

6 more elements

Dependencies are inferred from the claim text.

Description12,872 words

Summary2,816 words

#1. Field of the Invention

#Present invention relates to a control method of a semiconductor memory device and the semiconductor memory device having a successive data access operation, and in particular, a control method of a semiconductor memory device and the semiconductor memory device in which a pre-charge operation is required after completion of the successive access operation.

#2. Description of the Related Art

Brief description of the drawings15 figures

#FIG. 1 is an operational waveform diagram of successive access operation for illustrating principle of the present invention;

#FIG. 2 is a circuit block diagram showing data-input/output path of a semiconductor memory device directed to a first embodiment;

#FIG. 3 shows a circuit block diagram of a specific example of pre-charge control section directed to the first embodiment;

Detailed description9,797 words

#FIG. 1 shows an operational waveform diagram of successive access operation for illustrating principle of the present invention. Data of a plurality of bit lines connected to a plurality of memory cells due activation of a word line are set in a plurality of bit line pairs (BL0 and /Bl0, . . . , BLN and /BLN) and differentially amplified by sense amplifiers (not shown) up to voltage level of power source voltage VCC and ground voltage VSS. That is, when voltage level of the plurality of bit lines connected to the plurality of memory cells reach the power source voltage VCC or the ground voltage VSS, data-restore to each of the memory cells terminates and retention of data can be kept.

#When voltage level obtained by differential amplification at the bit line pairs (BL0 and /Bl0, . . . , BLN and /BLN) reaches predetermined voltage level, connection between a bit line pair selected by column selecting lines CL0, . . . , CLN and a data line pair (DB and /DB) is started. Voltage level of the data line pair (DB and /DB) is amplitude-limited in voltage. As a center value of amplitude-limited voltage, a voltage value is set to voltage level of (½) VCC. Therefore, when a bit line pair and a data line pair are connected, voltage level of the bit line pair receive voltage interference of the data line pair. For example, voltage level of bit lines BL0, . . . , BLN in high voltage level lowers whereas that of bit lines /BL0, . . . , /BL0 in low voltage level rises. That is, so-called disturb phenomenon occurs.

#As to voltage level of the bit line pairs (BL0 and /Bl0, . . . , BLN and /BLN) when connection is started, the voltage level against voltage interference due to disturb phenomenon may be amplification level that can avoid inversion of high-low voltage relation between bit lines. Not necessarily differential amplified up to full amplification level. In FIG. 1, a column selecting line CLO is driven in a form of pulse when differential amplification level of the bit line pair (BL0 and /BL0) reaches predetermined voltage so as to secure high-speed initial access for successive access operation.

Facts

Application

10/299,713Filed 20 Nov 2002

Priority

JP 2002-1063449 Apr 2002

Published

9 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 11/4094
Read-write [R-W] circuits: bit-line management or control circuits
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 11/4076
For memory cells of the field-effect type: timing circuits
G11C 11/4085
Address circuits: word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Timeline

9 Apr 2002Priority claimedJP 2002-106344
20 Nov 2002Application filedUS 10/299,713
20 Nov 2002Assigned to Fujitsu Limitedassignment of assignor's interest
9 Oct 2003Published
12 Dec 2008Assigned to Fujitsu Microelectronics Limitedassignment of assignor's interest
22 Jul 2010Assigned to Fujitsu Semiconductor Limitedchange of name
27 Apr 2015Assigned to Socionext Inc.assignment of assignor's interest

Control method of semiconductor memory device and semiconductor memory device

Life of this patent

Control method of semiconductor memory device and semiconductor memory device

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims25

Description12,872 words

Drawings

Classification6 codes

Life of this patent

Description12,872 words