Microinstruction pointer stack in a processor

#This invention relates to a microinstruction pointer stack in a processor.

#A microprocessor is a computer processor on a microchip. The microprocessor is typically designed to perform arithmetic and logic operations that make use of small number-holding areas called registers. Typical microprocessor operations include adding, subtracting, comparing, and fetching operands from memory or registers. These operations result from execution a set of instructions that comprise a program. The set of instructions are part of the microprocessor design.

#FIG. 1 is a block diagram of a processor.

#FIG. 2 is a block diagram of an executive environment of the processor of FIG. 1.

#FIG. 3 is a diagram of an out of order microinstruction pointer stack implemented in the out of order execution core of FIG. 1.

#Referring to FIG. 1 a processor 10 is shown. The processor 10 is a three way super scaler, pipelined architecture. Using parallel processing techniques, the processor 10 decodes, dispatches, and completes execution of (retire) three instructions per clock cycle. To handle this level of instruction throughput, the processor 10 uses a decoupled, e.g., twelve stage pipeline that supports out of order instruction execution. The pipeline of the processor 10 is divided into four sections, i.e., a first level cache 12, a second level cache 14, a front end 16, an out of order execution core 18, and a retire section 20. Instructions and data are supplied to these units through a bus interface unit 22 that interfaces with a system bus 24. The front end 16 supplies instructions in program order to the out of order execution core 18 that has very high execution bandwidth and can execute basic integer operations with one-half clock cycle latency. The front end 16 fetches and decodes instructions into simple operations called micro-ops (μops). The front end 16 can issue multiple μops per cycle, in original program order, to the out of order execution core 18. The front end 16 performs several basic functions. For example, the front end 16 performs prefetch instructions that are likely to be executed. The front end 16 decodes instructions into micro operations and generates micro code for complex instructions, delivers decoded instructions from an execution trace cache 26, and predicts branches using advanced algorithms in a branch prediction unit 28.

#The front end 16 of the processor 10 addresses some common problems in high speed, pipelined microprocessors. Two of these problems, for example, contribute to major sources of delays. These problems are the time to decode instructions fetched from the target and time wasted to decode instructions due to branches or branch targets that occur in the middle of cache lines.

#The execution trace cache 26 addresses both of these issues by storing decoded instructions. Instructions are fetched and decoded by a translation engine (not shown) and built into sequences of μops called traces. These traces of μops are stored in the trace cache 26. The instructions from the most likely target of a branch immediately follow the branch, without regard for continuity of instruction addresses. Once a trace is built, the trace cache 26 is searched for the instruction that follows that trace. If that instruction appears as the first instruction in an existing trace, the fetch and decode of instructions 30 from the memory hierarchy ceases and the trace cache 26 becomes the new source of instructions.