Multi-way select instructions using accumulated condition codes

#The present invention relates to processor architectures and instruction sets, and in particular, to processor architectures with instruction sets that provide multi-way select instructions using accumulated condition codes.

#In modem processors, execution of instructions occurs, in general, in the following sequential order: the processor reads an instruction, a decoder the processor decodes the instruction, and, then, the processor executes the instruction. In older processors the clock speed of the processor was generally slow enough that the reading, decoding and executing of each instruction could occur in a single clock cycle. However, modem microprocessors have improved performance by going to shorter clock cycles (that is, higher frequencies). These shorter clock cycles tend to make instructions require multiple, smaller sub-actions that can fit into the cycle time. Executing many such sub-actions in parallel, as in a pipelined and/or super-scalar processor, can improve performance even further. For example, although the cycle time of a present-day processor is determined by a number of factors, the cycle time is, generally, determined by the number of gate inversions that need to be preformed during a single cycle. Ideally, the execute stage determines the cycle time. However, in reality, this is not always the case. With the desire to operate at high frequency, the execute stage can be performed across more than one cycle, since it is an activity that can be pipelined. In a large number of workloads the added latency caused by the additional cycle(s) has only a small impact on processor performance. The ultimate goal of many systems is to be able to complete the execution of as many instructions as quickly and as efficiently as possible without adversely impacting the cycle time of the processor.

#One way to increase the number of instructions, or equivalent instructions, that can be executed is to create single instructions that can perform work that currently can only be accomplished by using multiple instructions without causing any timing problems during the execute phase. Instructions of this type can be especially effective in performing multi-way selects.

#FIG. 1 is a block diagram of a computer system that includes an architectural state including one or more processors, registers and memory, in accordance with an embodiment of the present invention.

#FIG. 2A is an exemplary structure of a processing core of the computer of FIG. 1 having a super-scalar and/or Very Long Instruction Word (VLIW) issue with multiple 2:1 multiplexers (MUXs) implemented in M consecutive execute stages for selecting a final source operand from every N source operands, where M=log2N in accordance with an embodiment of the present invention.

#FIG. 2B is an exemplary structure of a processing core of the computer of FIG. 1 having a super-scalar and/or Very Long Instruction Word (VLIW) issue with multiple 2:1 multiplexers (MUXs) implemented in 2 consecutive execute stages for selecting a final source operand from every four source operands, in accordance with an embodiment of the present invention.

#In accordance with an embodiment of the present invention, multi-way select instructions, for example, 4-way select, dual 4-way select and quad 4-way select as well as equivalent 8-way select, 16-way select, and/or 32 or more-way select instructions, may be implemented to execute in 2 cycles. Each of the above instructions also may be implemented using, for example, 2:1 multiplexers (MUXs) in each pipe stage. Similarly, 4:1 or 8:1 multiplexers may also be used, however, since the instructions are designed to consume the accumulated results of N-way Compare, MIN and/or MAX instructions, a succession of 2:1 MUX stages may be used. There may be multiple 2:1 multiplexer stages in each clock cycle, or the controls of multiple successive stages may be combined to drive a wider multiplexer, for example, a 4:1 or 8:1 multiplexer. Each 2:1 MUX may use predetermined condition codes to determine which of two source operands to select, where each instruction operand may provide a plurality of source operands that may be input to one or more MUXes. The condition codes may be generated, for example, by N-way, multiple-stage comparison and/or MAX/MIN instructions. The multi-way select instructions may operate in a fully pipelined manner (that is, with a throughput of one (1) instruction every cycle) and produce a result after log2N stages, which may be executed in log2N or fewer clock cycles. The multi-way select instructions may use a number of special purpose registers to control the selection of input source operands. The special purpose registers, definitions of which are specified below, merely illustrate one possible embodiment of the present invention and should not be construed as the only possible embodiment.

#In accordance with an embodiment of the present invention, the basic hardware that may be used by the multi-way select instructions may include M-bit multiplexers, which may be fitted easily in a single cycle of any processor. For example, since the blocks are of lower computational complexity, one (1) or more consecutive 2:1 multiplexers may be implemented in each execution stage without impacting the cycle time of the processor.

#In addition, implementing the whole operation in a single instruction may provide a significant savings in the pipeline front-end instruction supply requirements, since the functionality of multiple instructions may be packed into a single instruction without causing any timing problems during the execute stage.