Multiple-thread processor with in-pipeline, thread selectable storage

A method of operating a multi-threaded processor, the method comprising:

• executing plural threads;
• simultaneously representing, in a register file structure, register state for a least two of the threads;
• and
• simultaneously representing respective pipeline states for the two threads, the respective pipeline states being represented in a pipeline shared amongst the two threads using replicated thread selectable storage elements defined in the shared pipeline itself;
• and
• performing a rapid context switch between the two threads at least in part by freezing in the shared pipeline, for later resumption, active state of the shared pipeline and by resuming a previously frozen state of the shared pipeline.

A method of making a multi-threaded processor product, the method comprising:

• converting a single-thread processor core to a multiple-threaded processor core at least in part by substituting for pipeline registers that include single-bit flip-flops, respective multiple-bit pipeline registers embodied as collections of multiple-bit, thread-selectable flip-flops;
• maintaining substantially the same semiconductor footprint for the multiple-bit, thread-selectable flip-flops as for the single-bit flip-flops;
• and
• fabricating the multi-threaded processor product with the substituted multiple-bit, thread-selectable flip-flops.

An apparatus comprising:

• first means for simultaneously representing register state for a least two threads executing in a processor;
• and
• second means for simultaneously representing in a first pipeline, respective pipeline states for the two threads;
• wherein the pipeline state corresponding to one of the two threads is active and wherein the pipeline state corresponding to the other of the two threads is frozen therein.