Method and system for local memory addressing in single instruction, multiple data computer system

#The invention relates computer systems having multiple processors and a memory device, and, more particularly, to a method and system for allowing the memory device to be addressed either globally by a control unit or locally by each processor.

#The complexity of computer systems span the range from relatively simple systems having a single central processing unit (“CPU”) to systems having many processors that may operate somewhat independently of each other. One conventional multiple processor computer system is known as a single instruction, multiple data (“SIMD”) processor. In a SIMD processing system, multiple processors or processor elements (“PEs”) simultaneously perform the same operation on different items of data. As a result, SIMD processing systems are particularly useful for processing graphic images since graphic image processing typically involves performing a large number of identical operations on data that may differ from each other.

#The PEs in a SIMD processing system are generally coupled to a Central Control Unit that controls the operation of the PEs. The Central Control Unit generally transfers instructions defining the operations that will be performed by the PEs from a single program memory (not shown) into respective register files. The Central Control Unit also loads into the respective register file for each PE the data items that are to be operated on by the PE. Each PE can access its register file to read data, perform the operation on the data, and write results from the operation to the register file. The Central Control Unit can then read the results of all of the operations performed by the PEs by reading from all of the register files. Thus, the register files can be accessed by either the Central Control Unit or its respective PE.

#FIG. 1 is a block diagram of a conventional SIMD computer system.

#FIG. 2 is a block diagram of a SIMD computer system according to one embodiment of the invention.

#FIG. 3 is a block diagram and schematic of an address steering unit that is used in the SIMD computer system of FIG. 2.

#A SIMD computer system 50 according to one embodiment of the invention is shown in FIG. 2. The computer system 50 includes a Central Control Unit 52, which may be a conventional central processing unit (“CPU”) or microprocessor. The Central Control Unit 52 includes a data bus coupled to a data port of 32 SRAMs 561-5632. Each of the SRAMs 56 includes 8 SRAM arrays 58, each of which has 8 rows and 8 columns. Each column has 8 memory locations and can therefore store 8 bits. The Central Control Unit 52 also includes a 6-bit address bus 60 coupled to an address steering unit 64. The address steering unit selects certain bits of the 6-bit address to create a row address applied to a row address bus 66, and the remaining bits of the 6-bit address are used to create a column address that is applied to a column address bus 68. The row address bus 66 is coupled to a row decoder 70 that provides row select signals on a row select bus 72. As is well known in the art, the row select signals activate respective rows in the SRAMs 56 corresponding to the row address applied to the row decoder 70 by the address steering unit 64. The Central Control Unit 52 also includes a data bus 74 that is coupled to a respective data port of each SRAM 56. The Central Control Unit 52 also includes a number of signal lines (not shown) that are coupled to the SRAMs 62, but these have been omitted from FIG. 2 in the interest of clarity and brevity.

#As explained in greater detail below, the address steering unit 64 selects bits from the 6-bit address for a row address and a column address to load data and instructions into, and read data from, the SRAMs 56 in a several different formats. For example, by properly selecting bits to create a row address and a column address, 32-bit data word can be loaded into memory cells in the SRAM 56 in a single column spanning 4 rows.

#With further reference to FIG. 2, the computer system 50 includes 256 processing elements (“PEs”) 801-80256. Groups of 8 PEs 801-808 . . . 80249-80256 are coupled through respective write data buses 82 and read data buses 84 to respective SRAMs 561 . . . 5632. For example, the PEs 801-808 are coupled to the SRAM 561, as shown in FIG. 2. Each PE 80 is coupled to a respective one of the memory cell arrays 58. As mentioned above, each array 58 includes memory cells arranged in 8 rows and 8 columns, each of which stores 8 bits. Thus, since 8 arrays 58 are included in each SRAM 56, each SRAM 56 stores 4096 bits of data, and each PE 80 can access 512 bits of data in its respective 8 columns of its array 58.