Method and device to use memory access request tags

#The invention relates generally to system controller design for computer systems and, more particularly but not by way of limitation, to a device and method for tagging memory access requests with information identifying a characteristic of the system controller or requesting device.

#In personal computer systems (PCs) communication between various devices coupled to different buses and access to system memory is mediated by a single bridge or system controller circuit. Many bridge circuits also facilitate the maintenance of cache coherency operations by routing requests for access to system memory to a specified bus before relaying the request to memory. To fulfill these operational roles, the electrical and functional complexity of bridge circuits has increased dramatically.

#As the complexity of bridge circuit designs have increased it has become more difficult to troubleshoot (debug) the resulting devices. Often times, invasive techniques to extract signals representing the internal state of these devices must be obtained to facilitate system development and troubleshooting efforts. In addition, as the number, type and operational speed of devices seeking access to system memory increases conventional bridge circuits may fail to provide the necessary memory access bandwidth required.

#FIG. 1 shows a block diagram of a computer system in accordance with one embodiment of the invention.

#FIG. 2 shows a flow chart for a system controller operated in accordance with one embodiment of the invention.

#FIG. 3 shows a flow chart for a system controller operated in accordance with another embodiment of the invention.

#Techniques (including methods and devices) to provide improved memory access control mechanisms are described. The following embodiments of the invention, described in terms of a personal computer system having a PENTIUM® Pro processor bus, are illustrative only and are not to be considered limiting in any respect.

#Referring to FIG. 1, computer system 100 designed to utilize processor bus protocol signals to augment memory access operations is shown. Illustrative computer system 100 includes one or more host processors (only one is shown for convenience 102), one or more bus devices (only one is shown for convenience 104), system memory 106 and system controller or host bridge circuit 108. Processor 102 is coupled to system controller 108 via processor bus 110 and processor bus interface unit 112. Bus device 104 is coupled to system controller 108 via system bus 114 and bus interface unit 116. System memory 106 is coupled to processor 102 and bus device 104 via memory bus 118 and memory interface unit 120 of system controller 108. Illustrative system controller 108 employs switch 122 to route signals between processor 102, bus device 104 and memory 106.

#In one embodiment, processor 102 communicates with processor bus interface unit 112 over processor bus 110 using the PENTIUM® Pro or P6 bus communication protocol. (A description of the PENTIUM® Pro bus communication protocol may be found in the “Pentium Pro Family Developer's Manual, Volume 1: Specifications,” January 1996, available from Intel Corporation of Santa Clara, Calif.) One feature of the P6 protocol is the use of an 8-bit attribute field (denoted ATTR[7:0]#) during the second clock of a request phase operation.