Method, system, and apparatus for reducing power consumption of a memory

#The present invention relates to reducing power consumption of a memory.

#A Dynamic Random Access Memory, DRAM, is a typical memory to store information for computers and computing systems, such as, personal digital assistants and cellular phones. DRAMs contain a memory cell array having a plurality of individual memory cells; each memory cell is coupled to one of a plurality of sense amplifiers, bit lines, and word lines. The memory cell array is arranged as a matrix of rows and columns, and the matrix is further subdivided into a number of banks.

#The DRAM memory cell consists of a single transistor and a single capacitor and is dynamic because charge stored on the capacitor decays because of a various leakage current paths to surrounding cells and to the substrate. Typically, a refresh operation is performed on the DRAM memory cell to ensure the validity of the data. For example, the refresh operation is initiated by a memory controller to read the data from the cell array via the sense amplifiers and subsequently rewriting the data back into the cell array. Thus, the refresh operation restores the capacitor's charge to ensure the validity of the data.

#Subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. The claimed subject matter, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

#FIG. 1 is a schematic diagram in accordance with one embodiment.

#FIG. 2 is a schematic diagram in accordance with one embodiment.

#A system, apparatus, and method for reducing power consumption of a memory are described. In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention.

#An area of current technological development relates to achieving longer battery life for communication products and computer or computing systems by reducing power consumption. As previously described, reducing the memory's power consumption only occurs when the system or processor is also in a low power mode. In contrast, a method, apparatus, and system that incorporates a memory controller dynamically asserting the low power mode of the memory based at least in part on the pattern of accesses to the memory, rather than only when the system or processor is in low power mode, results in reduced power consumption of the memory.

#In one aspect, the claimed subject matter asserts a power down to allow for a low power mode of the memory based at least in part on a counter to track an idle status of a memory's row. In another aspect, the claimed subject matter asserts a power down to allow for a low power mode of the memory based at least in part on a least recently used status of a memory row and a predefined number of active memory rows. In yet another aspect, the claimed subject asserts a power down to allow for a low power mode of the memory based on at least in part on both the counter to track the idle status of a memory row and the least recently used status of a memory row. In still yet another aspect, the claimed subject asserts a low power mode of the memory based on at least in part on either pre-charging all the memory's pages that are in an open status of the row that will imminently enter a low power mode, but before de-asserting a clock enable (CKE ) pin, referred to as a pre-charge power down, or leaving the memory's pages in an open status before de-asserting the CKE pin. (hereinafter, referred to as a active power down).