Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration having an integrated memory

#1. Field of the Invention

#The present invention relates to an integrated memory having a memory cell array which contains a plurality of memory banks with respective memory cells. The invention further pertains to a circuit configuration having such an integrated memory.

#Integrated memory devices, for example in the form of so-called DRAMs (Dynamic Random Access Memories), are generally operated in a system environment containing, by way of example, a processor or a controller which accesses the memory for the purpose of reading stored data or for the purpose of writing data which are to be stored. An integrated memory, particularly in the form of a DRAM, generally contains a memory cell array which is normally divided into a plurality of separate memory banks containing respective memory cells. In each of the memory banks, a respective row decoder and column decoder can be used for separately accessing the memory cells, organized in matrix form, for the purpose of reading data or for the purpose of writing data. In memory systems containing a plurality of processors or controllers, it has been customary up to now for each processor or controller to access a dedicated memory connected to it. This can mean, firstly, a comparatively high space requirement and secondly a comparatively high cost involvement, since a respective dedicated memory chip needs to be provided for a plurality of processors or controllers.

#FIG. 1 is a block diagram of an embodiment of a circuit configuration according to the invention;

#FIG. 2 is a more detailed block diagram of an embodiment of an integrated memory and of a circuit configuration according to the invention; and

#FIGS. 3 to 8 are respective signal diagrams to explain the operation of the memory and of the circuit configuration shown in FIG. 2.

#Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown a circuit configuration containing an integrated memory 3 which has a plurality of memory banks B0 to B3 containing respective memory cells. The memory cells are diagrammatically indicated as a small memory field 4 of columns and lines. The memory 3 also has two connection panels P1 and P2 which can be operated independently of one another and which are connected to a respective communication bus 10 and 20 for the purpose of external communication by the memory. Each of the communication buses 10 and 20 can be connected to each of the memory banks B0 to B3, shown symbolically by respective switch symbols that can be actuated by a control circuit 30.

#FIG. 2 shows a more detailed embodiment of the memory 3 and of the circuit configuration shown in FIG. 1. Each of the independently operable connection panels P1 and P2 is connected to a respective command and address bus 11, 21 and to a respective data bus 12, 22. The command and address bus 11 is used for transmitting command signals CMD#1 and address signals ADD#1 and is connected to the connection panel P1. The data bus 12 is used for transmitting data signals DQ#1 and is likewise connected to the connection panel P1. The command and address bus 21 is used for transmitting the command signals CMD#2 and address signals ADD#2 and is connected to the connection panel P2. The data bus 22 is used for transmitting the data signals DQ#2 and is likewise connected to the connection panel P2. The command and address bus 11 and the data bus 12 are connected to the processor unit 1, and the command and address bus 21 and the data bus 22 are connected to the processor unit 2. The respective data bus 12, 22 can be connected to each of the memory banks B0 to B3, likewise shown symbolically by switch symbols in FIG. 2.

#The memory 3 contains a control circuit 30 which controls changeover of the data buses 12, 22 for the purpose of connection to the respective memory banks B0 to B3 and also controls access to the memory cells in the respective memory banks B0 to B3. The control circuit 30 is connected to the respective command and address bus 11, 21. The control circuit 30 also produces a number of first control signals BSY#0 to BSY#3 which corresponds to the number of memory banks B0 to B3. The control signals BSY#0 to BSY#3 are respectively associated with one of the memory banks and respectively indicate if the associated memory bank is being accessed. In addition, the control circuit 30 produces a number of second control signals CNT#1, CNT#2 which corresponds to the number of connection panels P1, P2. One of the control signals CNT#1, CNT#2 is produced if an access collision occurs between access to one of the memory banks via one of the connection panels P1, P2 and access to the same memory bank via the respective other one of the connection panels P1, P2. The control signals BSY#0 to BSY#3 and CNT#1, CNT#2 are made available on external connections of the memory 3 and are tapped off by the processor units 1 and 2. These respectively receive the control signals and access the memory 3 independently of one another on the basis of these control signals.