Microprocessor with repeat prefetch instruction

A microprocessor, comprising:

• an instruction decoder, for decoding instructions in an instruction set, said instruction set comprising at least a set of instructions defined by an Intel Pentium III processor, said instruction set further comprising a repeat prefetch instruction;
• and
• said repeat prefetch instruction comprising:
• a Pentium III PREFETCH instruction opcode;
• a Pentium III REP string instruction prefix preceding said opcode;
• and
• a count specifying a number of cache lines to be prefetched.

A microprocessor in a system with a system memory, the microprocessor comprising:

• an instruction decoder, for decoding a prefetch instruction specifying a count of cache lines to prefetch from the system memory and an address in the system memory of said cache lines;
• an address register, coupled to said instruction decoder, for storing said address specified in said prefetch instruction;
• a count register, coupled to said instruction decoder, for storing said count specified in said prefetch instruction;
• and
• control logic, coupled to said address register, configured to control the microprocessor to prefetch said cache lines specified in said address register and said count register from the system memory into a cache memory of the microprocessor.

A method of a microprocessor prefetching cache lines into its cache, the method comprising:

• (a) detecting a repeat prefetch instruction specifying a count of cache lines for prefetching from a system memory address;
• (b) copying said count from a general purpose register of the microprocessor to a prefetch count register;
• (c) storing said address in a prefetch address register;
• (d) prefetching a cache line specified by said prefetch address register into the cache;
• (e) decrementing said prefetch count register;
• (f) incrementing said prefetch address register;
• and
• (g) repeating said steps (d), (e), and (f) until said prefetch count register reaches a zero value.