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US 2003/0191897 A1Published application
Instruction cache apparatus and method using instruction read buffer
AssigneeFaraday Technology Corp.
InventorMin-Cheng Kao
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AssigneeFaraday Technology Corp.
InventorMin-Cheng Kao
Estimating the term…
The present invention provides an instruction cache apparatus and method using the instruction read buffer. The apparatus comprises an instruction hit analysis unit, an instruction read buffer, a first cache instruction word memory, a second cache instruction word memory, a first multiplexer and a second multiplexer. The instruction hit analysis unit receives a programmable counter output signal, compares this with a plurality of tags, and after the analysis, outputs the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. The second multiplexer reads the expected instruction word from one of either the first cache instruction word memory, the second cache instruction word memory or the first multiplexer according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. While the bus interface waits for the next demanded instruction word to reply to the instruction read buffer, it writes an instruction line into the first or the second cache instruction word memory. Wherein, the instruction line is in the instruction read buffer and includes the previously expected instruction word.
An instruction cache apparatus using the instruction read buffer, comprising:
An instruction cache apparatus using the instruction read buffer, comprising:
An instruction cache method using the instruction read buffer, used for an instruction cache system, comprising:
Dependencies are inferred from the claim text.
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Instruction prefetching: implementation provisions of instruction buffers, e.g. prefetch buffer; banks
Concurrent instruction execution, e.g. pipeline or look ahead: instruction prefetching
Overlapped cache accessing, e.g. pipeline: with reload from main memory
Caches characterised by their organisation or structure: with two or more cache hierarchy levels
Term end not estimated
1. Field of Invention
The present invention generally relates to an instruction cache apparatus and method, and more particularly, to an instruction cache apparatus and method using the instruction read buffer (IRB).
2. Description of Related Art
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention. In the drawings,
FIG. 1 schematically shows a partial circuit diagram of the conventional cache apparatus;
FIG. 2 schematically shows a connection relationship diagram of the conventional instruction read buffer;
The concept of the present invention is to add a new path, a new counter and a new comparator, to achieve the objective of increasing the instruction hit rate and reducing the time wasted writing into the cache apparatus when the instruction miss occurs.
FIG. 3 schematically shows a partial circuit diagram of a cache apparatus 119 using the instruction read buffer of the preferred embodiment according to the present invention. The apparatus of the instruction read buffer of the present invention comprises the instruction read buffer (IRB) 102, the cache instruction word memory 106, the cache instruction word memory 107, the multiplexer 104, and the instruction hit analysis unit 120. The multiplexer 104 is controlled by the cache instruction word memory instruction hit signal 124 (i.e. the instruction hit signal of the cache instruction word memory 106 or 107) and the instruction read buffer instruction hit signal 122 that are output from the instruction hit analysis unit 120, to fetch the instruction word stored in the cache instruction word memory 106 or the cache instruction word memory 107 or the instruction read buffer 102. The instruction hit analysis unit 120 comprises the first tag determine unit, the second tag determine unit, the instruction read buffer determine unit, and the OR gate 114 that is used to receive the output from those three units mentioned above.
The present invention particularly arranges to add an output path to the multiplexer 103. Thus, the instruction word temporarily stored in the instruction read buffer 102 can be read directly via the multiplexer 103 to the multiplexer 104. That is, the input of the multiplexer 104 includes the instruction word from the instruction read buffer 102 directly. Moreover, the method of the instruction read buffer 102, whereby it writes the instruction word output from the bus interface unit 101 into the cache instruction memory word 106 or 107 via the multiplexer 103, is different from the conventional method. As shown in FIG. 2, the instruction read buffer 102 is a line that is capable of storing four instruction words. The conventional arrangement writes the instruction word temporarily stored in the instruction read buffer 102 into the cache instruction word memory 106 or 107 via the multiplexer 103 in a manner of one instruction word at a time and so the writing of the instruction word is divided in four times. However, the present invention is particularly arranged to write the instruction word temporarily stored in the instruction read buffer 102 into the cache instruction word memory 106 or 107 via the multiplexer 103 in the manner of one line at a time, that is, four instruction words can be written in one time.