Data-cache data-path

#The present invention relates to a pipelined processor generally and, more particularly, to a data-path for a data-cache within the processor.

#Performance of a pipelined processor is determined in part by the speed at which data is moved through the memory stage of a data pipeline. A basic operation of the memory stage is to store and load data to and from a data-cache memory. A specific operation of a data-path associated with the data-cache memory includes byte-aligning or shifting the data for presentation to a central processor unit. Other specific operations of the data-path include driving a local data bus and gathering data from multiple sources for presentation to the data-cache memory. Each of the above operations has a potential to introduce delays that can ultimately affect the performance of the pipelined processor.

#The architecture of the data-path before and after the data-cache memory influences the performance of the memory stage of the data pipeline. The data-path leading into the data-cache memory can degrade performance by presenting the data such that each store operation constrains access to the data-cache memory for multiple run cycles. The data-path following the data-cache memory can also degrade performance by delaying presentation of data read from the data-cache memory to other devices within the processor.

#These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:

#FIG. 1 is a block diagram illustrating a processor implementing a preferred embodiment of the present invention;

#FIG. 2 is a block diagram of a circuit implementing a data-cache data-path; and

#Referring to FIG. 1, a block diagram illustrating a processor 100 implementing a preferred embodiment of the present invention is shown. The processor 100 generally comprises a circuit 102 and a central processing unit (CPU) 104. The circuit 102 may be a data-cache data-path. The circuit 102 is generally configured to (i) shift, (ii) present, and (iii) store the data items to and from the CPU 104. The CPU 104 may be configured to (i) receive data items, (ii) execute the data items, and (iii) present the resulting data items. The term “data item” may be used in a generic sense in this document. A data item may include, but is not limited to information, control, data, signal, trigger, value, parameter, operator, operand, and the like.

#The CPU 104 may have an output 106 that may connect to an input 108 of the circuit 102 through a CPU data output bus (e.g., CPU_DATAOUT). The CPU 104 may also have an input 110 that may connect to an output 112 of the circuit 102 through a CPU data input bus (e.g., CPU_DATA_IN). The CPU_DATAOUT bus may contain data items presented by the CPU 104. The CPU_DATA_IN bus may contain data items presented by the circuit 102.

#The processor 100 may comprise a number of circuits other than the CPU 104 that require access to the circuit 102 to store and receive data. For example, the processor 100 may comprise, but is not limited to, one or more of a bus interface unit (BIU) 114, a system coprocessor 116, a first coprocessor 118, a second coprocessor 120, one or more memory mapped registers (MMR) 122, and a test interface 124. The system coprocessor 116 may be referred to as a coprocessor zero (CPO). The test interface 124 may be, in one example, a boundary scan test interface in accordance with the Enhanced Joint Test Action Group Standard IEEE-1149.1 (published by the Institute of Electrical and Electronics Engineering, Inc., New York, N.Y.), the relevant portions of which are incorporated by reference.