Buffer controller and management method thereof

#1. Field of Invention

#The invention relates to a buffer controller and management method thereof. More explicitly, the invention provides a buffer controller that utilizes a new linked structure to manage the allocation and release of a buffer memory and the corresponding buffer management method.

#2. Related Art

#The present invention will become more fully understood from the detailed description given hereinbelow illustration only, and thus are not limitative of the present invention, and wherein:

#FIG. 1 is a block diagram showing the connection between a buffer and a controller in the prior;

#FIG. 2 is a schematic diagram of conventional buffer management using a linked list;

#With reference to FIG. 4, the buffer memory 30 contains a free list comprising a plurality of buffer registers in series. Each buffer register has a corresponding link node 31, which has a field as the pointer for linking.

#In the first embodiment of the invention, a switch controller uses a buffer controller. The buffer controller controls a buffer memory to temporarily store packets of transmitting data. The buffer controller 20 has a head pointer 50 and a tail pointer 51. After initialization, the pointers 50, 51 point to the first address 30.0001 and the last address 30.2048 of a free list, respectively. Preferably, the buffer controller 20 contains a cache memory 52 for pointing to available buffer registers, so cache memory 52 stores the addresses of available buffer registers. In the free list, the buffer register 30.0001 uses its link node to point to the next buffer register 30.0002; the buffer register 30.0002 uses its link node to point to the next buffer register 30.0003. Such links continue until the last buffer register 30.2048. The link node of the last buffer register 30.2048 points to null, indicating the end of the free list.

#In a second embodiment of the invention, suppose the cache memory 52 embedded in the buffer controller of the switch controller has three cache units. These cache units can be embedded SRAM units, flip-flops, or registers. When the switch controller is initialized, the addresses 30.0001, 30.0002, 30.0003 are stored in the cache memory 52 and the head pointer 50 points to the address 30.0004. When allocating a memory space, the addresses of available buffer registers are assigned for the allocation from the cache memory 52 with a priority. As previously planned, each buffer register thus obtained has a size of 128 bytes. If the incoming packets are small ones (the smallest has 64 bytes), the system only needs to ask the cache memory 52 for allocating one buffer register. After using the buffer register, the address of the buffer register released will be stored in the cache memory 52. In this case, the head pointer 50 is rarely used. This means that the number of SRAM access actions is effectively reduced.