Source controlled cache allocation

#1. Field of the Invention

#This invention is related to the field of caches and, more particularly, to allocation of space in caches.

#2. Description of the Related Art

#The following detailed description makes reference to the accompanying drawings, which are now briefly described.

#FIG. 1 is a block diagram of one embodiment of a system.

#FIG. 2 is a timing diagram illustrating transactions on a bus shown in FIG. 1, including a cache allocate signal.

#While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

#System Overview

#Turning now to FIG. 1, a block diagram of one embodiment of a system 10 is shown. Other embodiments are possible and contemplated. In the embodiment of FIG. 1, the system 10 includes processors 12A-12B, an L2 cache 14, a memory controller 16, a pair of input/output (I/O) bridges 20A-20B, and various I/O interface circuits 22A-22I. The system 10 may include a bus 24 for interconnecting the various components of the system 10. As illustrated in FIG. 1, each of the processors 12A-12B, the L2 cache 14, the memory controller 16, and the I/O bridges 20A-20B are coupled to the bus 24. Thus, each of the processors 12A-12B, the L2 cache 14, the memory controller 16, and the I/O bridges 20A-20B may be an agent on the bus 24 for the illustrated embodiment. The I/O bridge 20A is coupled to the I/O interface circuits 22A-22B (specifically, in the illustrated embodiment, a Peripheral Component Interconnect (PCI) interface circuit 22A and a Lightning Data Transport (LDT) interface circuit 22B (where the LDT interface is now also being referred to as the HyperTransport interface), and the I/O bridge 20B is coupled to the I/O interface circuits 22C-22I (specifically, in the illustrated embodiment, three network interface circuits 22C-22E, two serial interface circuits 22F-22G, a system management bus (SMBus) Interface circuit 22H, and a Personal Computer Memory Card International Association (PCMCIA) Interface circuit 22I). The L2 cache 14 is coupled to the memory controller 16, which is further coupled to a memory 26.