Method and system for dynamically operating memory in a power-saving error correction mode

A method of operating a dynamic random access memory (“DRAM”) device in a power-saving mode, comprising:

• reading a set of data bits from each of a plurality of groups of memory cells in the DRAM device;
• generating a respective set of check bits corresponding to each of the sets of data bits read from each group of memory cells;
• storing the sets of check bits in the DRAM device;
• after a delay, reading each set of data bits and corresponding sets of check bits from the memory cells;
• generating a set of syndrome bits derived from each of a respective set of data bits read from the DRAM device and from the corresponding set of check bits read from the DRAM device;
• determining from each of the sets of syndrome bits if any of the respective set of read data or read check bits is in error;
• if the syndrome indicates any bits of the read data is in error, correcting the error to generate corrected data;
• if the syndrome indicates any of the check bits is in error, correcting the error to generate corrected check bits;
• writing any corrected data to the DRAM device;
• and
• writing any corrected check bits to the DRAM device.

A scrubbing controller for operating a dynamic random access memory (“DRAM”) device, comprising:

• an error correcting code (“ECC”) generator/checker coupled to a data bus of the DRAM device, the ECC generator/checker being operable to determine if an ECC applied to the ECC generator/checker through the data bus contains at least one error, and, if so, to generate a corrected ECC;
• an addressing device coupled to an address bus of the DRAM device, the addressing device generating a sequence of row addresses for the DRAM device;
• a control device coupled to a control bus of the DRAM device, the control device being operable to cause data to be written to and read from the DRAM device at an address corresponding to a row address generated by the addressing device;
• and
• a timer triggering the control device to cause at least one ECC to be read from the DRAM device after a delay period, and, if the ECC generator/checker determines that the read ECC contains at least one error, to write to the DRAM device a corresponding corrected ECC generated by the ECC generator/checker, the delay period established by the timer being longer than a period required to refresh memory cells of the DRAM device without generating any errors.

A computer system, comprising:

• a central processing unit (“CPU”);
• a dynamic random access memory (“DRAM”) device having a data bus, an address bus, and a control bus;
• a system controller coupled to the CPU, the system controller including a memory controller coupled to the DRAM device through the data bus, address bus and control bus;
• and
• a scrubbing controller coupled to the DRAM device through the data bus, address bus and control bus, the scrubbing controller comprising:
• an error correcting code (“ECC”) generator/checker coupled to a data bus of the DRAM device, the ECC generator/checker being operable to determine if an ECC applied to the ECC generator/checker through the data bus contains at least one error, and, if so, to generate a corrected ECC;
• an addressing device coupled to an address bus of the DRAM device, the addressing device generating a sequence of row addresses for the DRAM device;
• a control device coupled to a control bus of the DRAM device, the control device being operable to cause data to be written to and read from the DRAM device at an address corresponding to a row address generated by the addressing device;
• and
• a timer triggering the control device to cause at least one ECC to be read from the DRAM device after a delay period, and, if the ECC generator/checker determines that the read ECC contains at least one error, to write to the DRAM device a corresponding corrected ECC generated by the ECC generator/checker, the delay period established by the timer being longer than a period required to refresh memory cells of the DRAM device without generating any errors.

A dynamic random access memory (“DRAM”) device, comprising:

• an array of memory cells arranged in rows and columns;
• an addressing circuit receiving and decoding an external address;
• a data path coupling data between a data bus and memory cells corresponding to the decoded memory address;
• a command decoder receiving and decoding external memory commands, the command decoder generating control signals for controlling the operation of the DRAM device;
• and
• a scrubbing controller comprising:
• an error correcting code (“ECC”) generator/checker coupled to a data path of the DRAM device, the ECC generator/checker being operable to determine if an ECC applied to the ECC generator/checker through the data path contains at least one error, and, if so, to generate a corrected ECC;
• an addressing generator generating a sequence of row addresses for the DRAM device;
• a control device operable to cause data to be written to and read from the DRAM device at an address corresponding to a row address generated by the addressing device;
• and
• a timer triggering the control device to cause at least one ECC to be read from the DRAM device after a first delay period, and, if the ECC generator/checker determines that the read ECC contains at least one error, to write to the memory array a corresponding corrected ECC generated by the ECC generator/checker, the first delay period established by the timer being longer than a period required to refresh the memory cells of the DRAM device without generating any errors.