On-chip cache redundancy technique
OwnerChandra Thimmanagari, Jui-Cheng Suinventors
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Abstract
A technique for operating a cache memory in one of multiple modes is provided. The technique involves using an fuse dependent control stage to control the generation of read and write enable signals to redundantly implemented tag and data arrays such that a portion of the cache memory may be effectively used even if another portion of the cache memory is defective due to malfunction, yield issues, process variations, etc.
Claims21
An integrated circuit, comprising:
- a cache memory comprising a tag array and a data array;
- a control stage;
- first circuitry, responsive to the control stage, that generates signals to the tag array;
- and
- second circuitry, responsive to the control stage, that generates signals to the data array,
- wherein the control stage determines whether the cache memory operates in any one of a first mode and a second mode,
- wherein operation in the first mode allows use of a full address space of the cache memory, and
- wherein operation in the second mode allows use of a portion of the full address space of the cache memory.
A cache memory configurable by a fuse dependent control stage, the cache memory comprising:
- a tag array responsive to first circuitry dependent on the fuse dependent control stage;
- and
- a data array responsive to second circuitry dependent on the fuse dependent control stage,
- wherein the fuse dependent control stage determines whether the cache memory operates in one of a first mode and second mode,
- wherein operation in the first mode allows use of a full address space of the cache memory, and
- wherein operation in second mode allows use of a portion of the full address space of the cache memory.
An integrated circuit, comprising:
- memory means for storing data, wherein the memory means is capable of operating in any one of a first mode and a second mode;
- generating means for generating read and write enable signals to the memory means;
- and
- control means for determining a mode of operation for the memory means, wherein the generating means is responsive to the control means.
A method for performing cache memory operations, comprising:
- determining whether to operate a cache memory in any one of a first mode and second mode;
- selectively controlling a state of circuitry based on the determination;
- generating control signals to the a array dependent on the state of the circuitry;
- and
- generating control signals to a data array dependent on the state of the circuitry,
- wherein operation in the first mode allows use of a full address space of the cache memory, and wherein operation in the second mode allows use of a portion of the full address space of the cache memory.
Dependencies are inferred from the claim text.