Bus system and information processing system including bus system

A bus system comprising:

• a first bus connected to first interface means via a first control command line and a first data line having first bit width;
• a second bus connected to second interface means via a second control command line and a second data line having second bit width;
• a common control command bus commonly connecting said first and second control command lines and transmitting common command information;
• data conversion means performing conversion of bit width between said data lines having different bit widths;
• and
• an arbitration circuit performing arbitration for bus right of said first and second buses in response to an arbitration request from said first and second interface means.

A bus system comprising:

• a first write bus connected to first interface means via a first write control command line and a write data line having first bit width;
• a first read bus connected to said first interface means via a first read control command line and a read data line having the first bit width;
• a second write bus connected to second interface means via a second write control command line and a write data line having second bit width;
• a second read bus connected to said second interface means via a second read control command line and a read data line having second bit width;
• a first common control command bus commonly connecting said first write control command line and said second write control command line;
• a second common control command bus commonly connecting said first read control command line and said second read control command line;
• a write data conversion circuit to which said first write bus and said second write bus are connected and performing conversion of bit width between these write buses;
• a read data conversion circuit to which said first read bus and said second read bus are connected and performing conversion of bit width between these read buses;
• a first arbitration circuit performing arbitration of bus right for said first and second write buses in response to a demand from said first and second interfaces;
• and
• a second arbitration circuit performing arbitration of bus right for said first and second read buses in response to a demand from said first and second interfaces.

A bus system comprising:

• n in number of buses connecting master side interface means and slave side interface means via control command lines and data lines and having mutually different bit widths;
• a common control command bus commonly connecting respective control command lines of n in number of buses;
• a data conversion circuit connected to data lines of respective of n in number of buses and performing conversion of bit width between different bit widths;
• and
• an arbitration circuit simultaneously performing arbitration for said n in number of buses.

A bus system comprising:

• a first bus having a data line of first bit width;
• a first unit connected to said first bus;
• a second bus having a data line of second bit width;
• a second unit connected to said first bus;
• an arbitration circuit simultaneously performing arbitration for said first bus and said second bus when command is output from said first unit to said second unit;
• a conversion circuit performing converting operation between said first bit width and said second bit width between said first bus and said second bus;
• and
• a common control command bus connecting said first bus and said second bus.