Method and device for arbitrating bus grant

#The present invention relates to a method for arbitrating bus grant, and more particularly to a method for arbitrating bus grant among a plurality of master devices. The present invention also relates to an arbiter for bus grant.

#Please refer to FIG. 1 which is a schematic diagram illustrating the transmission among a plurality of master devices 111, 112, . . . , 11n and a plurality of target devices 121, 122, . . . , 12n via a shared bus 10. In order to coordinate the data transmission, an arbiter 13 is provided between the master devices 111, 112, . . . , 11n and the shared bus 10 to arbitrate the bus grant to which of the master devices in a certain period. Generally, a fixed priority or a Round-Robin mechanism is employed for the arbitration of the shared bus architecture.

#In order to increase the utility rate of the shared bus 10, a retry mechanism is also widely applied to the current bus protocol, e.g. a peripheral component interconnect (PCI) bus protocol. That is, when the dominating one of the master devices, for example the master device 111, outputs a data transfer request signal to the target device 121 but the target device 121 cannot achieve the data transaction at that time, the target device 121 will output a retry signal to the master device 111. In response to the retry signal, the arbiter 13 will rearrange the bus grant order. In other words, the master device 111 has to wait a certain period of time to become a candidate for the bus grant again. When it is the turn again of the master device 111 to dominate the shared bus 10, a data transfer request signal is re-outputted to the target device 121. By this way, the shared bus 10 will not be idly occupied by the incomplete data transaction between the master device 111 and the target device 121.

#The present invention may best be understood through the following description with reference to the accompanying drawings, in which:

#FIG. 1 is a schematic diagram illustrating the conventional transmission among a plurality of master devices and a plurality of target devices via a shared bus;

#FIG. 2 is a schematic waveform diagram illustrating a conventional retry mechanism for use with a PCI bus;

#The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.

#Please refer to FIG. 3. A plurality of master devices 211, 212, . . . , 21n and a plurality of target devices 221, 222, . . . , 22n are interconnected via a shared bus 20. An arbiter 23 is used for coordinating the bus grant. The arbiter 23 includes a plurality of timer devices 231, 232, . . . , 23n in communication with the master devices 211, 212, . . . , 21n, respectively. Those timer devices 231, 232, . . . , 23n are implemented by counters in this embodiment. After one of master devices 211, 212, . . . , 21n, e.g. the master device 211, outputs a data transaction signal, e.g. a data transfer request signal, the corresponding timer device, i.e. the timer device 231, starts to accumulatively count from an initial value. When the requested data transfer is done, the outputs of the master device 211 and one of the target devices, e.g. the target device 221, indicate a data transfer completion signal so as to reset the timer device 231 to the initial value. When a preset threshold value is counted up, it means that the master device 211 has waited for a long time since it requested a data transfer. Therefore, a predetermined dominating index of the master device 211, which relates to the bus-utility preference for the master device 211 to access to the shared bus 20, is re-estimated. For example, an assigned priority of the master device 211 is enhanced and/or an assigned transaction period of time thereof is prolonged. The above arbitrating method is summarized in the flowchart of FIG. 4.

#When the shared bus 20 is, for example, a peripheral component interconnect (PCI) bus, the data transfer completion signal includes a target ready signal (TRDY) and an initiator ready signal (IRDY), both at low levels. In other words, when detecting that both the signal TRDY from the target device 221 and the signal IRDY from the master device 211 are at the low levels, the arbiter 23 determines that the data transfer of the master device 211 is completed. Hence, the time accumulation value of the corresponding timer device 231 is reset to the initial value, e.g. zero, and later on, the corresponding timer device 231 re-starts to count in response to another data transfer request signal from the master device 211.