I2C repeater with voltage translation

#1. Field of the Invention

#The invention relates to devices for transferring signals between buses. More particularly, it relates to voltage translation and address multiplexing between different buses.

#2. Description of the Related Art

#FIG. 1 shows a prior art system for communicating between a system device and various memory components.

#FIG. 2 shows a system of the present invention for communicating between a system component and various memory components.

#FIG. 3 shows a logic diagram of a repeater circuit for a data line.

#FIG. 2 shows a system 2 of the present invention. System component 10 initiates communications with multiple memory data components (MDC) 12 over bus 14. System component 10 may have various forms. For instance, it might be an integrated circuit dedicated to the functions described herein, or it might be a processor which also performs many other functions. Each MDC 12 can communicate over its respective bus 18 with any device 16 connected to that bus, such as synchronous dynamic random access memories (SDRAM). In one embodiment, bus 18 and SDRAMs 16 can be the same devices shown in the prior art of FIG. 1. The voltage used on bus 14 should be chosen for compatibility with system component 10, such as 1.8 volts. The voltage used on bus 18 should be chosen for compatibility with memory components 16, such as 3.3 volts. FIG. 2 shows four MDCs 12, with eight SDRAMs 16 per MDC, although other quantities can also be used. Buses 14 and 18 can both be I2C buses. In one embodiment, each MDC 12 can perform several functions, including 1) voltage translation between bus 14 and bus 18, 2) multiplexing of address data between bus 14 and bus 18, and 3) manipulation of the clock line between bus 14 and bus 18 to accommodate slow slave devices. Each MDC can function as a repeater by receiving logic signals on one bus and duplicating those logic signals on the other bus, even if each bus operates at a different voltage level. Each MDC has a data circuit 30 for processing the data signals, a clock circuit 60 for processing the clock signals, and a control circuit 90 for providing overall control of the MDC. In the embodiment shown in FIG. 2, each MDC is identical except for its bus address on bus 14.

#FIG. 3 shows a circuit 30 for processing data signals SDA for an I2C bus, while FIG. 5 shows a circuit 60 for processing clock signals SCL for an I2C bus. Bus 14 contains a bi-directional data line 13 and a bi-directional clock line 17. Bus 18 contains a bi-directional data line 15 and a bi-directional clock line 19.

#FIG. 3 shows a data circuit 30 for processing the signals between data line 13 of bus 14 and data line 15 of bus 18. Data port 32 includes a line driver output 36 coupled to data line 13, a line driver input 37 which is coupled to a predetermined logic level, and a line driver input 38 which is coupled to data line 15. Selector input 34 can select either of inputs 37 or 38, depending on the logic state presented to selector input 34. Enable input 33 can be used to enable the selected input to be fed to output 36, or to disable output 36 so that neither input is fed to output 36, again depending on the logic state presented to enable input 33. Data port 39 provides a similar circuit for connection to data line 15, with line driver output 46 coupled to data line 15, a line driver input 47 coupled to a predetermined logic level, and a line driver input 48 coupled to data line 13. Selector input 44 can select either of inputs 47 or 48, depending on the logic state presented to selector input 44. Enable input 43 can be used to enable the selected input to be fed to output 46, or to disable output 46 so that neither input is fed to output 46, depending on the logic state presented to enable input 43. Data ports 32 and 39 are shown to contain a two-input multiplexer and a line driver. These are shown to illustrate internal functionality, and should not be read as a requirement for a specific internal circuit design.