Method and apparatus for implementing single/dual packed multi-way addition instructions having accumulation options

#The present invention relates to processor architectures and instruction sets, and in particular, to processor architectures with instruction sets that provide single/dual packed multi-way addition instructions having accumulation options.

#In modern processors, in general, in the following sequential order: the processor reads an instruction, a decoder in the processor decodes the instruction, and, then, the processor executes the instruction. In older processors the clock speed of the processor was generally slow enough that the reading, decoding and executing of each instruction could occur in a single clock cycle. However, modem microprocessors have improved performance by going to shorter clock cycles (that is, higher frequencies). These shorter clock cycles tend to make instructions require multiple, smaller sub-actions that can fit into the cycle time. Executing many such sub-actions in parallel, as in a pipelined and/or super-scalar processor, can improve performance even further. For example, although the cycle time of a present-day processor is determined by a number of factors, the cycle time is, generally, determined by the number of gate inversions that need to be preformed during a single cycle. Ideally, the execute stage determines the cycle time. However, in reality, this is not always the case. With the desire to operate at high frequency, the execute stage can be performed across more than one cycle, since it is an activity that can be pipelined. In a large number of workloads the added latency caused by the additional cycle(s) has only a small impact on processor performance. The ultimate goal of many systems is to be able to complete the execution of as many instructions as quickly and as efficiently as possible without adversely impacting the cycle time of the processor.

#One way to increase the number of instructions, or equivalent instructions, that can be executed is to create a single instruction that can perform work that currently can only be accomplished by using multiple instructions without causing any timing problems during the execute phase. An instruction of this type can be especially effective in performing multiple additions both with and without accumulation of the results of the additions.

#FIG. 1 is a block diagram of a computer system that includes an architectural state including one or more processors, registers and memory, in accordance with an embodiment of the present invention.

#FIG. 2 is an exemplary structure of a processing core of the computer of FIG. 1 having a super-scalar and/or Very Long Instruction Word (VLIW) issue with multiple 3:1 adders implemented in two consecutive execute stages, in accordance with an embodiment of the present invention.

#FIG. 3 is a top-level flow diagram of a method for providing an accumulatable packed multi-way addition instruction in a processor, in accordance with an embodiment of the present invention.

#In accordance with an embodiment of the present invention, single/dual packed multi-way addition instructions having accumulation options may be implemented to execute in 2 cycles using, for example, 3:1 adders to perform the addition and conditional accumulation. For example, a 2-way addition instruction may be implemented using a multiplexer in the first pipe stage and a 3:1 adder in the second pipe stage to perform the addition and conditional accumulation. The instruction may operate in a fully pipelined manner (that is, with a throughput of one instruction every cycle) and produce a result after two (2) cycles. Similarly, for example, in accordance with another embodiment of the present invention, a 4-way addition instruction may be implemented using a multiplexer followed by a 2:1 adder in the first pipe stage and a 3:1 adder in the second pipe stage to perform the addition and conditional accumulation. Both the 2-way instruction and the 4-way instruction also may use a number of special purpose registers to determine the polarity of operands, the definitions of which are specified below merely to illustrate one possible embodiment of the present invention. Likewise, both instructions also may produce and store multiple flags into one or more of the special purpose registers, the operation of the 3:1 adders may be dynamically controllable at runtime, and any data generated during the execution of either of the 2-way and/or 4-way instruction may determine the operation of subsequent instructions.

#In accordance with an embodiment of the present invention, the basic hardware that may be used by the multi-way addition instructions may include 8-bit and 16-bit adders, which may be fitted easily in a single cycle of any processor. This is especially true if the processor on which the instructions are running operates on higher precision data types such as 64-bit integers and floating point numbers. For example, since the adders are of lower computational complexity, two 3:1, 16-bit adders may be implemented in 2 consecutive execute stages without impacting the cycle time of the processor.

#In addition, implementing the whole operation in a single instruction may provide a significant savings in the pipeline front-end instruction supply requirements, since the functionality of multiple instructions may be packed into a single instruction without causing any timing problems during the execute stage.