Debug function built-in type microcomputer

#1. Field of Invention

#The present invention relates to a debug function built-in type microcomputer, and more particularly to a debug function built-in type microcomputer with an enhanced bus tracing method.

#2. Description of Related Art

#FIG. 1 is a schematic that shows a debug system using a debug function built-in type microcomputer in accordance with the present invention;

#FIG. 2 is a schematic that shows a related art output method of outputting bus information at the time of tracing;

#FIG. 3 is a schematic that shows an output method at the time of compressing positive data in accordance with the present invention;

#A debug function built-in type microcomputer in accordance with the present invention is described in detail below with reference to the accompanying drawings.

#FIG. 1 is a schematic that shows main parts of a debug system using a debug function built-in type microcomputer in accordance with an exemplary embodiment of the present invention. FIG. 1 shows a CPU 1, a BCU (bus control unit) 2, a DBG (debug unit) 3, a memory 4, an external debug tool 5, and a personal computer 6 to perform debugging. Also, FIG. 1 shows a cache memory 22, and a DMA 23. The CPU 1, BCU 2, DBG 3, cache memory 22 and DMA 23 are built in a chip of a microcomputer 10. The microcomputer 10 in FIG. 1 corresponds to the microcomputer 71 in FIG. 10, the CPU 1 and BCU 2 together correspond to the processor core 74 in FIG. 10, the DBG 3 corresponds to the debug unit 75 in FIG. 10, the memory 4 to the memory 72 in FIG. 10, and the external debug tool 5 and the personal computer to perform debugging 6 together correspond to the PC host computer 81. Although the input/output control circuit 73 is not shown in FIG. 10, it is placed in parallel with the memory 4.

#The CPU 1 and the BCU 2 are connected through a command address bus 11, a command bus 12, a data address bus 13, a data bus 14, a read/write signal 15 and an access size signal 16. Each of the buses 11-14 has a 32-bit width for transfer. The BCU 2 and the memory 4 are connected through a 32-bit parallel data address bus 17, a data bus 18 and a read/write signal line 19. In FIG. 1, the BCU 2 is connected to a destination that is represented by the memory 4. However, in addition to the memory 4, the data address bus 17 and the data bus 18 may also connect to a peripheral unit and an external memory outside the user target system through an input/output interface not shown in FIG. 1, and send addresses and data to them and receive data from them. Furthermore, the BCU 2 also exchanges data with the cache 22 and the DMA 23. These addresses and data are switched by a signal judgment selection circuit 21 within the BCU 2 and exchanged.