Exception handling method and apparatus for use in program code conversion
AssigneeThe Victoria University of Manchester
InventorsAlasdair Rawsthorne, John H. Sandham, Jason Souloglou
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AssigneeThe Victoria University of Manchester
InventorsAlasdair Rawsthorne, John H. Sandham, Jason Souloglou
Estimating the term…
A method of handling exceptions for use in an emulator (20) performing program code conversion. Registers (X) of a subject machine (11) being emulated (20) are represented by a pair of abstract registers (XA,XB) on the target machine (31), suitably using memory locations of the target machine and/or any available target registers. One of the pair (e.g., Reg XA) holds a definitive value at entry into a section (100) of subject code (10) while the other (e.g., Reg XB) holds a speculative value which is updated during translation and execution of that section of code. Exceptions are handled by recovering the conditions of the virtual subject machine (11) upon entry into the section of subject code (100) using the definitive version of each abstract register (i.e., Reg XA). Advantageously, the function of the pair of registers (XA,XB) is alternated upon successful completion of each section of subject code (100) such that a definitive version of each register is always available for exception handling while avoiding time consuming copy and storing operations.
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A method of representing a subject register in an emulator (20), the method comprising the steps of:
A method for use in handling exceptions by an emulator performing program code conversion between subject code suitable for a subject processor and target code suitable for a target processor, the method comprising the steps of:
An emulator apparatus, comprising:
An emulator apparatus for performing program code conversion between subject code suitable for a subject processor and target codes suitable for a target processor, the emulator apparatus comprising:
A computer program product containing computer readable instructions for performing a method of representing a subject register in an emulator, the method comprising the steps of:
A computer program product containing computer readable instructions for performing program code conversion between subject code suitable for a subject processor and target codes suitable for a target processor, the method comprising the steps of:
Dependencies are inferred from the claim text.
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Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines: abstract…
Computing and data processing
Term end not estimated
The present invention relates in general to the field of program code conversion for computer systems and in particular, but not exclusively, to the field of emulation using dynamic binary translation.
A program for a computer takes several different forms. Typically a program is written first in a high-level language readily understood by a human programmer. The program is compiled from the high-level language into a low-level language more appropriate for control of a computer's processor and related components. However, in order for the processor to function, the program code must be provided in a machine-readable form that directs primitive operations of the processor such as loading, shifting, adding and storing operations. To run faster, some processors use an expanded set of instructions each of which represent a sequence of primitive instructions. This is known as a complicated instruction set computer (CISC). However, program code written (or compiled) specifically for a first processor with a particular instruction set in most cases cannot run on any other type of processor because of differences between the instruction set for each type of processor.
An emulator allows program code written for a processor of a first type (a “subject” processor) to be run on a processor of a second type (a “target” or “host” processor). One form of this emulation process is known as binary translation because executable binary code appropriate to the subject processor is translated into executable binary code appropriate to the target processor.
For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:
FIG. 1 shows a typical prior art configuration for a subject processor;
FIG. 2 shows a typical emulator using binary translation;
Referring to FIG. 1 a typical prior art arrangement is shown illustrating the configuration of a subject machine wherein subject code 10 is executed directly on a subject processor 11. Suitably the subject code is executable binary code. However, the subject code may be represented in any suitable language with intermediate layers (compilers, etc.) between the subject code 10 and the subject processor 11 as will be familiar to the skilled person.
Referring now to FIG. 2, a typical prior art configuration is shown to illustrate the use of a binary translation type emulator 20 as an intermediate layer enabling the subject code 10 to be executed by a target processor 31. The preferred embodiment of the present invention is particularly intended for use with an emulator 20 which performs dynamic binary translation of the subject code 10 into target code 30 executable on the target processor 31.
Referring now to FIG. 3 the emulator 20 of the preferred embodiment is illustrated in more detail and comprises a front end 21, a core 22 and a back end 23.