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AssigneeInternational Business Machines Corporation
InventorsAndrew Douglas Davies, Daniel Lawrence Stasiak
Estimating the term…
A method and apparatus are provided for implementing dynamic noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits. A method of logical effort is applied to the CMOS logic circuits. Selected circuits within the CMOS logic circuits are checked for noise immunity utilizing a noise test simulation to identify each selected circuit failing the noise test simulation. An electrical effort is fixed to a value for providing noise immunity for each identified selected circuit failing the noise test simulation. The method of logical effort is applied to each remaining selected circuit not failing the noise test simulation. The sequential steps are repeated for each remaining selected circuit not failing the noise test simulation until no selected circuit failing the noise test simulation is identified. The selected circuits that are checked for noise immunity include, for example, dynamic circuits and passgate circuits. When none of the selected circuits fail the noise test simulation, or the electrical efforts have been fixed for all of the selected circuits failing the noise test simulation, the delay through the CMOS logic circuits has been minimized and the selected circuits are all assured of adequate noise immunity.
A computer implemented method for implementing noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits comprising the steps of:
Apparatus for implementing noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits, said apparatus including a plurality of computer executable instructions stored on a computer readable medium, wherein said instructions, when executed by said computer, cause the computer to perform the steps of:
A computer implemented method for implementing noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits comprising the steps of:
Dependencies are inferred from the claim text.
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Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Computing and data processing
Term end not estimated
The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing dynamic noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits.
The method of logical effort is a recent addition to the field of designing CMOS logic circuits that provides a way to minimize the delay of a CMOS circuits using the simple concepts of logical effort, electrical effort, and effort delay. The method of logical effort specifies a method of choosing the sizes of the transistors in these circuits such that the delay from the input to the output of the circuit is minimized. This method therefore has a wide application to CMOS design, and is easily implemented in software.
The method of logical effort is described in the book entitled “Logical Effort: Designing Fast CMOS Circuits” by Ivan Sutherland, Bob Sproull and David Harris, copyright 1999 by Academic Press. The method has a serious drawback when the circuits include dynamic circuits and other circuits that are susceptible to noise problems.
The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
FIG. 1 is a block diagram representation illustrating a computer system for implementing dynamic noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits in accordance with the preferred embodiment;
FIGS. 2 and 3 are flow charts illustrating exemplary sequential steps for implementing dynamic noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits in accordance with the preferred embodiment;
Having reference now to the drawings, in FIG. 1, there is shown a computer or data processing system of the preferred embodiment generally designated by the reference character 100. As shown in FIG. 1, computer system 100 includes a central processor unit (CPU) 102, a read only memory 103, a random access memory or main memory 104, and a display adapter 106 coupled to a display 108. CPU 102 is connected to a user interface (UI) adapter 110 connected to a pointer device and keyboard 112. CPU 102 is connected to an input/output (10) adapter 114 connected to a direct access storage device (DASD) 116 and a tape unit 118. CPU 102 is connected to a communications adapter 120 providing a communications function.
Various commercially available processors could be used for computer system 100, for example, an IBM personal computer or similar workstation can be used. An example of a specific computer system on which the invention may be implemented is the International Business Machines Corp. RS/6000 computer system. Central processor unit(s) 102 is suitably programmed to execute the flowcharts of FIGS. 2 and 3, for implementing noise immunity and minimizing delay of logical complementary metal oxide semiconductor (CMOS) circuits in accordance with the preferred embodiment.
In accordance with features of the preferred embodiment, by implementing an algorithm of the invention as illustrated in FIG. 2, dynamic noise immunity is added to the method of logical effort, that assures dynamic noise immunity as well as minimizing the delay through the circuit. The algorithm is simple and can be easily implemented in software.