Simulating program instruction execution and hardware device operation

Apparatus for simulating data processing operations performed by a data processing apparatus, said data processing apparatus including a processor core operable to execute program instructions and a plurality of hardware devices coupled to said processor core, said apparatus comprising:

• a hardware simulator operable to simulate said plurality of said hardware devices, said hardware simulator being responsive to one or more stimulus signals to generate one or more response signals simulating a response of one or more of said plurality of hardware devices to said one or more stimulus signals if applied to one or more of said plurality of hardware devices;
• an instruction set simulator operable to simulate said processor core, said instruction set simulator being responsive to one or more stimulus signals to simulate execution of one or more program instructions by said processor core and to generate one or more response signals simulating a response of said processor core if said one or more program instructions were executed by said processor core;
• a test scenario manager coupled to said hardware simulator and said instruction set simulator and operable to generate said stimulus signals supplied to said hardware simulator and said instruction set simulator such that said test scenario manager acts as a master to command simulation operations performed by said hardware simulator and said instruction set simulator in accordance with predetermined test scenario parameters.