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AssigneeNone recorded
InventorsAlexander Roger Deas, Igor Anatolievich Abrosimov
Estimating the term…
A distributed terminator for terminating a transmission line linking a plurality of integrated circuits. The terminator comprises a plurality of resistors and a capacitor that is usually an ESD structure. The values of the resistors are such that the reflection co-efficient of the combined termination is lower across the bandwidth of the signal being transmitted than a reflection coefficient with a termination using resistors in the same topology where the effective value of the resistors is equal to the line impedance.
A distributed terminator for terminating a transmission line having its end linked to an integrated circuit, the terminator comprising a parallel-connected resistor means connected in parallel to said integrated circuit and a series resistor means connected in series to the transmission line and said integrated circuit.
A data communication apparatus comprising a transmission line connected to an integrated circuit via a driver incorporated therein, where the transmission line is terminated by a terminator comprising a parallel-connected resistor means connected in parallel to said driver and a series resistor means connected in series to the transmission line and said driver.
A data communication apparatus comprising a transmission line connected to an integrated circuit via a receiver incorporated therein, where the transmission line is terminated by a terminator comprising a parallel-connected resistor means connected in parallel to said receiver and a series resistor means connected in series to the transmission line and said receiver.
A method of terminating a transmission line having its end connected to an integrated circuit, the method including the following steps:
Dependencies are inferred from the claim text.
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Arrangements for coupling to transmission lines: arrangements for impedance matching
Digital communication
Term end not estimated
1. Technical Field
The present invention relates to the communication of signals, in particular, to the transmission and reception of digital signals, where the signals are at such a frequency that they are distorted by the non-linear behaviour of the package parasitics and ESD (Electrostatic Discharge) protection structures within the receiver.
The present invention is particularly applicable to interfaces between integrated circuits and for high speed communications, such as currently addressed by Asynchronous Transfer Mode (ATM), Gigabit Ethernet, 3GIO, RapidIO, Hyperchannel and Fibre Transmission Channels, and makes possible yet higher data rates for a particular bandwidth of the transmission medium.
A detailed description of the present invention will now be given, without loss of generality, and with reference to the following figures:
FIG. 1a shows a typical prior art termination scheme for a receiver.
FIG. 1b shows a simplified general termination scheme according to the invention.
Specific features and advantages of the present invention will become apparent from a detailed description of the present invention as compared to the prior art.
In FIG. 1a, a typical prior art termination circuit is shown schematically, in which a transmission line having impedance Zo and connected to a receiver having a parasitic capacitance C is terminated by a parallel-connected resistor R matching the impedance Z0 of the transmission line. The behaviour of the prior art circuits is illustrated by curve “a” in FIG. 2, which shows a drastic decrease of the module of characteristic impedance Z at high frequencies, as defined by the following formula: 1 | Z in | = R √ 1 + ( 2 π F max RC ) 2 ∼ 1 2 π F max RC
From this formula, the turning point (seen in FIG. 2) of curve “a” where the characteristic impedance starts to decrease can roughly be estimated as: 2 F decr = 1 2 π Z 0 C