Test fixture for semiconductor packages and test method of using the same

#The present invention relates to test fixtures for semiconductor packages and test methods of using the test fixtures, and more particularly, to a test fixture for use with BGA (ball grid array) semiconductor packages, and a method for testing the semiconductor packages through the use of the test fixture.

#Conventionally, fabricated semiconductor packages are electrically connected by a test fixture to a test device e.g. a test oven for performing various functional tests, such as direct current test, bum-in test, room/cold test, hot sort test, etc; these tests are used to test functionality of the semiconductor packages, for selecting good-quality packages and eliminating inferior products, thereby assuring yield of package fabrication. Since the above functional tests are conventional in the art, they are not to be further described herein.

#FIGS. 1A and 1B illustrate BGA (ball grid array) semiconductor packages 10 mounted on a circuit board 11 of a conventional test fixture, for electrically connecting the semiconductor packages 10 through the text fixture to a test device (not shown) where functional tests are performed. As shown in the drawings, the circuit board 11 is formed with a plurality of contact terminals 12 that are adapted to be in contact with solder balls 13 acting as input/output (I/O) connections of the semiconductor packages 10. Each of the contact terminals 12 is provided with three contacts for use to hold a corresponding solder ball 13 in position; since such a three-contact design is conventional in the art, it is not further to be described herein. Therefore, with electrical contact between solder balls 13 of the semiconductor packages 10 and contact terminals 12 formed on the circuit board 11, by electrically connecting I/O ports 14 of the circuit board 11 to the test device, the semiconductor packages 10 can be electrically coupled to the test device where desirable functional tests are performed.

#The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:

#FIG. 1A (PRIOR ART) is a perspective view of a conventional test fixture for accommodating semiconductor packages thereon;

#FIG. 1B (PRIOR ART) is a cross-sectional view of the conventional test fixture of FIG. 1A mounted with semiconductor packages;

#Preferred embodiments for a test fixture proposed in the present invention are described in more detail as follows with reference to FIGS. 2 to 4. The drawings only illustrate components or parts of the test fixture in simplicity; it should be understood that, these components or parts are not drawn in real sizes or numbers, and the test fixture of the invention is structurally more complex in practical fabrication.

#FIG. 2 illustrates components of a test fixture 2 of the invention; FIG. 3 illustrates the test fixture 2 of the invention mounted with semiconductor packages 20. As shown in the drawings, the test fixture 2 is used to electrically connect a plurality of semiconductor packages 20 e.g. BGA (ball grid array) semiconductor packages to a test device (not shown) where functional tests are performed for the semiconductor packages 20.

#The test fixture 2 comprises: a first circuit board 21 formed on a surface 210 thereof with a plurality of contact mechanisms 211, and adapted to be electrically connected to the test device; a second circuit board 22 having an upper surface 220 and a lower surface 221 opposed to the upper surface 220, wherein the upper surface 220 is adapted for accommodating a plurality of semiconductor packages 20 thereon, and the lower surface 221 is mounted on the contact mechanisms 211 of the first circuit board 21 in a manner that, the second circuit board 22 is interposed between the semiconductor packages 20 and the first circuit board 21, allowing the semiconductor packages 20 to be electrically connected to the first circuit board 21 and the test device by the second circuit board 22; an interposer 23 mounted on the upper surface 220 of the second circuit board 22, and formed with a plurality of through holes 230 that penetrate through the interposer 23, so as to allow the semiconductor packages 20 mounted on the second circuit board 22 to be received in the through holes 230; and a covering member 24 mounted on the interposer 23, for covering the semiconductor packages 20 received in the through holes 230, wherein a plurality of elastic mechanisms 241 are formed on the covering member 24 corresponding in position to the through holes 230 of the interposer 23, and adapted to be interposed between the covering member 24 and the semiconductor packages 20.