Method of patterning dielectric layer with low dielectric constant
AssigneeUnited Microelectronics Corp.
InventorsTing-Chang Chang, Po-Tsun Liu, Jeng-Tzong Sheu
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AssigneeUnited Microelectronics Corp.
InventorsTing-Chang Chang, Po-Tsun Liu, Jeng-Tzong Sheu
Estimating the term…
The invention relates to a method for directly patterning a low-k dielectric layer by a high energy flow without using any photoresist layer, so that the exposed portion of the low-k dielectric layer is cured and becomes insoluble to the developing solution. The unexposed portion of the low-k dielectric layer remains soluble to the developing solution and will be removed in the developing process. The performance and reliability of the devices are improved and the fabrication processes are simplified.
A method for patterning a low-k dielectric layer, comprising:
A method for forming an opening in a low-k dielectric layer, comprising:
Dependencies are inferred from the claim text.
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By modifying materials of the dielectric parts: by irradiating with electromagnetic or particle radiation
Of inorganic materials: by chemical means
Of organic materials: by chemical means
By forming openings in the dielectric parts: for dual-damascene structures
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1. Field of Invention
The present invention relates to a method of patterning a dielectric layer. More particularly, the present invention relates to a method of patterning a dielectric layer with a low dielectric constant k.
2. Description of Related Art
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
FIG. 1 shows a prior-art copper damascene plug structure manufactured by the conventional via-first damascene process;
FIG. 2A through FIG. 2E are schematic, cross-sectional views showing process steps for patterning low-k material layers for a dual damascene opening according to one preferred embodiment of the invention; and
Various type of advanced lithographies for IC fabrication have been proposed, including ultraviolet light lithography, electron beam lithography, ion beam lithography and x-ray lithography. Optical exposure lithography is capable of approximately 1 micron resolution and 0.5 micron registration, while electron beam lithography is primarily used to produce photomasks and has 0.5 micron resolution with 0.2 registration. X-ray lithography has a resolution as high as 10-100 angstroms and ion beam lithography has a resolution of approximately 100 angstroms. However, none of these lithographies has been proposed to direct dielectric layer exposure without using photoresist layers. The present invention ingeniously proposes that the aforementioned advanced lithographies are applied directly to pattern the dielectric layer without using intermediate photoresist layers.
Herein, “directly” means that the high energy flow is used to pattern the low-k dielectric layer without using any photoresist layer. In the case of x-ray and short electromagnetic waves, photomasks having desired patterns thereon are used for pattern transferring. However, photomasks can be omitted if ion beam or electron beam is used as the high energy flow.
The present invention uses a high energy flow to directly pattern the low-k dielectric layer without using photoresist layers as masks in the photolithography steps. The high energy flow applying on the spin-on low-k dielectric material can be x-rays, electron beams, ion beams or any other short electromagnetic waves with high energy. Preferably, the high energy flow has an energy density of about 10 W/cm2 to 150 W/cm2. Particularly, the present invention is suitable to be applied in devices with a geometry of less than 0.1 microns.