Method for forming barrier layer

#1. Field of Invention

#The present invention relates to a method of fabricating an integrated circuit (IC). More particularly, the present invention relates to a method of fabricating a barrier applied in contact/via plugs.

#2. Description of Related Art

#The file of this patent contains at least one drawing executed in color. The Patent and Trademark Office upon request and payment of the necessary fee will provide copies of this patent with color drawing(s).

#The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

#FIG. 1 is a cross-sectional view of a portion of a semiconductor substrate including a barrier layer according to one preferred embodiment of the present invention;

#FIG. 1 is a cross-sectional view of a portion of a semiconductor substrate including a barrier layer according to one preferred embodiment of the present invention. First, as shown in FIG. 1, a semiconductor substrate 100 having a component layer 101 formed thereon is provided. The component layer 101 comprises at least one conductive region 102 and at least one isolation structure 103. The component layer 101 can further comprises one or more transistor components (not shown) and/or one or multiple metallic layers (not shown). The isolation structure 103 is, for example, a field oxide layer or a shallow trench isolation structure. A dielectric interlayer 104 formed on the substrate 100 covers the isolation structure 103 and the underlying conductive region 102. The conductive region 102 can be a polysilicon gate layer or a source/drain region of one of the transistors, or a metallic layer. For silicon-based semiconductor devices, dielectric materials for the dielectric interlayer 104 can be silicon dioxide, possibly doped with phosphorus, boron/phosphorus or arsenic, formed by conventional processes to the typical thickness employed in this technology.

#The dielectric interlayer 104 is then patterned and etched down to form an opening 106 that exposes the conductive region 102. If the conductive region 102 is a polysilicon gate layer or a source/drain region of one of the transistors in the component layer 101, the opening 106 is a contact opening. If the conductive region 102 is a metallic layer in the component layer 101, the opening 106 is a via opening.

#In accordance with the invention, a barrier layer 108 is formed in the opening 106 to ensure good adhesion and good electrical contact of subsequent layers to the underlying conductive region 102. The barrier layer 108 is a composite layer consisting of a titanium layer 108a and a titanium nitride layer 108b. The stoichiometric ratio of the titanium nitride layer 108b is not limited to 1:1, but dependent on the requiring electrical and physical properties. The barrier layer 108 is also a diffusion barrier layer. Finally, a conductive material layer 110 is formed on the barrier layer 108 and fills the opening 106. Preferred examples of such conductive materials include CVD or bias sputtered tungsten or molybdenum. An extra portion of the conductive material layer 110 is then removed by either planarization or dry etching. Thereafter, an anti-refractive coating layer (not shown) is formed on the remained conductive material layer 110, if necessary. The following processes for completing the plug manufacture are known to people in the art, and thus will not be described in details.