Semiconductor device and its manufacturing method

#The present invention relates to field effect transistors including a heterojunction for a channel region, and more particularly relates to countermeasures against variation in threshold voltage of a field effect transistor.

#In recent years, portable communication terminals represented by cellular phones are widely used. Such portable terminals are generally driven by batteries and it is strongly desired to reduce power consumption without sacrificing operation speed in portable terminals in order to prolong the lifetime of batteries. To achieve a portable communication terminal with low power consumption without reducing operation speed, it is effective to increase drain saturation current to maintain current driveability while lowering threshold voltage to reduce supply voltage in the portable terminal. To satisfy such demands, there have been many studies on heterojunction MOS transistors (which will be hereinafter called “hetero MOS”) using as a channel region a material with high-mobility carriers.

#In a known MOS transistor, carriers travel along the interface between a gate oxide film and a silicon substrate. Energy level largely fluctuates around the interface between the gate oxide film that is an amorphous layer and the silicon substrate that is a crystal layer. Because of the energy level fluctuation, carriers are easily affected by interface scattering in the known MOS transistor, resulting in problems such as reduction of carrier mobility and increase in noise.

#FIG. 1 is a view illustrating the cross-sectional structure of a hetero MOS in accordance with the present invention.

#FIG. 2 is a graph showing the correlation between threshold voltage and the thickness of an Si cap region for a known hetero MOS and the hetero MOS of the present invention.

#FIGS. 3(a) through 3(c) are graphs showing band profiles at zero bias in three types of hetero MOS devices having the impurity profiles used for the simulations of FIG. 2.

#Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. For the sake of simplicity, components common to the embodiments are identified by the same reference numerals.

#(Embodiment 1)

#First, the structure of a hetero MOS in accordance with this embodiment will be described. FIG. 1 illustrates the cross-sectional structure of a p-channel hetero MOS 10 of this embodiment in which a SiGe layer is used as a channel region and an Si/SiGe heterojunction is utilized.