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US 2003/0190781 A1Published application
Memory masking for periphery salicidation of active regions
AssigneeSGS-Thomson Microelectronics S.A.
InventorsRobert Louis Hodges, Loi Ngoc Nguyen
Life of this patent
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Abstract
An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.
Drawings
Claims28
An integrated circuit memory, comprising:
- an array of memory cells;
- and
- peripheral circuits, include sense amplifiers and address decode logic, connected to provide data access to said cells from external pins;
- wherein at least some portions of said peripheral circuits include field-effect transistors having gates formed from a patterned conductive thin-film layer and having source/drain regions of a first conductivity type which are clad with a self-aligned metal silicide layer;
- and
- wherein at least some portions of said memory cells include field-effect transistors having gates formed from said conductive thin-film layer and having source/drain regions of said first conductivity type which are not clad with a self-aligned metal silicide layer.
3 more elements
An integrated circuit memory, comprising:
- an array of memory cells, individual ones of said cells being connected to be powered by first and second supply voltages, and including
- a pair of field-effect driver transistors having source/drain regions thereof provided by diffusions in a substantially monocrystalline semiconductor material, said driver transistors being cross-coupled to pull a pair of complementary data nodes toward said first supply voltage;
- a pair of load elements connected to pull at least one of said data nodes toward said second supply voltage;
- and
- at least one pass transistor connected to selectably provide access to one of said data nodes;
- and
- peripheral circuits, include sense amplifiers and address decode logic, connected to provide data access to said cells from external pins;
- wherein at least some portions of said peripheral circuits include field-effect transistors having source/drain regions thereof provided by diffusions in said semiconductor material which are clad with a self-aligned metal silicide layer;
- and wherein said source/drain regions of said driver transistors are not clad with a self-aligned metal silicide layer.
6 more elements
An integrated circuit memory, comprising:
- an array of memory cells, individual ones of said cells being connected to be powered by first and second supply voltages, and including
- a pair of field-effect driver transistors having source/drain regions thereof provided by diffusions in a substantially monocrystalline semiconductor material, said driver transistors being crosscoupled to pull a pair of complementary data nodes toward said first supply voltage;
- a pair of load elements connected to pull at least one of said data nodes toward said second supply voltage;
- and
- at least one pass transistor connected to selectably provide access to one of said data nodes;
- peripheral circuits, include sense amplifiers and address decode logic, connected to provide data access to said cells from external pins;
- wherein at least one said supply voltage is routed to said cells through diffusions which are clad with a self-aligned metal silicide layer;
- and wherein said source/drain regions of said driver transistors are not clad with a self-aligned metal silicide layer.
5 more elements
An integrated circuit memory, comprising:
- an array of memory cells,
- individual ones of said cells including field-effect transistors having source/drain regions thereof provided by diffusions in a substantially monocrystalline semiconductor material,
- individual ones of said cells being connected to be powered by first and second supply voltages;
- and
- peripheral circuits, include sense amplifiers and address decode logic, connected to provide data access to said cells from external pins;
- wherein at least one said supply voltage is routed to said cells through diffusions which are clad with a self-aligned metal silicide layer.
3 more elements
A fabrication method, comprising the steps of:
- (a.) providing a substrate having monocrystalline semiconductor material in active areas, at a first surface thereof, which are laterally separated by isolation regions;
- (b.) forming a patterned gate layer overlying and capacitively coupled to portions of ones of said active areas, in locations which define transistor portions of memory cells and also define transistor portions of peripheral logic;
- (c.) forming self-aligned dielectric spacers along the edges of said thin-film layer;
- and
- (d.) depositing and reacting a metal on at least some ones of said active areas, to form a metal silicide at the surfaces of said active areas;
- wherein a masking step is used in connection with said step (d.), in locations such that said step (d.) ultimately provides said metal silicide in said transistor portions of said peripheral logic, but not in said transistor portions of said memory cells.
3 more elements
A fabrication method, comprising the steps of:
- (a.) providing a substrate having monocrystalline semiconductor material in active areas, at a first surface thereof, which are laterally separated by isolation regions;
- (b.) forming a patterned gate layer overlying and capacitively coupled to portions of ones of said active areas, in locations which define transistor portions of memory cells and also define transistor portions of peripheral logic;
- (c.) forming self-aligned dielectric spacers along the edges of said thin-film layer;
- and
- (d.) depositing and reacting a metal on at least some ones of said active areas, to form a metal silicide at the surfaces of said active areas;
- wherein a masking step is used in connection with said step (d.), in locations such that said step (d.) ultimately provides said metal silicide in said transistor portions of said peripheral logic, but not in said transistor portions of said memory cells.
3 more elements
Dependencies are inferred from the claim text.