US 2003/0190779 A1 · Method of fabricating mosfet transistors with multiple threshold voltages by halo compensation and masks

Abstract

An apparatus including a MOSFET circuit having duel threshold voltage NMOS and PMOS transistors wherein the threshold voltage of a low threshold NMOS transistor is set with a first halo implant, a threshold voltage of a high threshold voltage PMOS transistor is set with a second halo implant, and, a threshold voltage of a high threshold voltage NMOS transistor is enhanced while, a threshold voltage of a low threshold voltage PMOS transistor is compensated with a third halo implant.

Claims4

Dependent claims

An apparatus comprising:

a MOSFET circuit having duel threshold voltage NMOS and PMOS transistors wherein the threshold voltage of a low threshold NMOS transistor is set with a first halo implant, a threshold voltage of a high threshold voltage PMOS transistor is set with a second halo implant, and, a threshold voltage of a high threshold voltage NMOS transistor is enhanced while, a threshold voltage of a low threshold voltage PMOS transistor is compensated with a third halo implant.

Dependencies are inferred from the claim text.

Facts

Application

10/426,440Filed 30 Apr 2003

Priority

2 Jan 2002

Published

9 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 62/371
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels

Abstract

Facts

Application

10/426,440Filed 30 Apr 2003

Priority

2 Jan 2002

Published

9 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 62/371
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels

Method of fabricating mosfet transistors with multiple threshold voltages by halo compensation and masks

Life of this patent

Abstract

Claims4

Method of fabricating mosfet transistors with multiple threshold voltages by halo compensation and masks

Life of this patent

Abstract

Claims4