Method for the fabrication of a DMOS transistor

#Field of the Invention

#The present invention relates to a method for the fabrication of a DMOS transistor, in particular, to a method for the fabrication of a DMOS transistor that is integrated with a CMOS logic in a semiconductor component.

#In many applications of modern electronic products, the problem arises that, in addition to the pure processing of information, the electronic product also has to act in some form on its environment. Applications of this type include a very wide range of products. One example that may be mentioned is the control system of an airbag, which, on one hand, evaluates the measurement signals from an acceleration sensor and, on the other hand, in the event of an accident, triggers the airbag. A further example is an intelligent charger for recharging batteries.

#FIGS. 1A to 1F are fragmentary, diagrammatic, cross-sectional views illustrating a series of process steps for producing a transistor configuration according to the prior art;

#FIGS. 2A to 2F are fragmentary, diagrammatic, cross-sectional views illustrating a series of process steps for producing a transistor configuration according to the invention.

#Referring now to the figures of the drawings in detail and first, particularly to FIGS. 2a to 2f thereof, there is shown a diagrammatically depiction of steps of a method according to the invention for the fabrication of a DMOS transistor structure. To fabricate the DMOS transistor structure, a semiconductor substrate 1 is provided, on which the insulation 2 between the individual transistors and the gate oxide 3 have already been produced. Furthermore, all the well regions, buried regions and deep diffusion required for the complete fabrication of a DMOS transistor and of CMOS transistors have already been produced. Then, a conductive layer, preferably, a polysilicon layer 4 is deposited, and an insulation layer 5 is deposited on the polysilicon layer 4. Next, the polysilicon layer 4 and the insulation layer 5 are patterned by photolithography so that the polysilicon layer 4 is opened up substantially only in the source region (FIG. 2A). All the other regions, in particular, the regions in which CMOS transistors are to be produced subsequently, remain covered by the polysilicon layer 4.

#Then, dopant implantation for fabrication of the body region and of the source region is carried out. The implantations of body 8 and source 9 are masked by the patterned polysilicon layer 4. In the process, first of all, the dopant for the body region is implanted and is driven into the semiconductor substrate 1 by a heat treatment. Then, the dopant for the source region is implanted and is driven into the semiconductor substrate 1 by a second heat treatment. This has the advantage over conventional methods in that the source implantation can be carried out without additional outlay after the body diffusion. This reduces the density of crystal defects and facilitates optimization of the source doping. Preferably, oxidation 13 to seal the open polysilicon flank takes place at the start of the first heat treatment (furnace step) (FIG. 2B).

#Then, the source region and the remaining polysilicon regions are covered by a protective layer 14 (FIG. 2C). In the present example, the protective layer 14 includes three individual layers, namely, a silicon oxide layer 14a, a silicon nitride layer 14b, and a further silicon oxide layer 14c. All three layers are, preferably, produced with the aid of CVD processes. It is particularly preferable if the two silicon oxide layers 14a, 14c are produced by a TEOS process.