Sub-milliohm on-chip interconnection

#(1) Field of the Invention

#The invention relates to interconnect techniques in an integrated circuit device, and more particularly, to a very low resistivity interconnection method and structure using bonded metal wires.

#(2) Description of the Prior Art

#In the accompanying drawings forming a material part of this description, there is shown:

#FIG. 1 illustrates an exemplary cross section of a prior art integrated circuit device.

#FIG. 2 illustrates a simplified model of the circuit of FIG. 1.

#The preferred embodiments disclose a novel method and structure for reducing the resistivity of an interconnect in an integrated circuit device. The method and structure uses bonded metal wires, or stitches, on internal integrated circuit nodes to reduce resistivity of couplings. It should be clear to those experienced in the art that the present invention can be applied and extended without deviating from the scope of the present invention.

#Referring now to FIG. 3, the preferred embodiment of the present invention is illustrated. Several important features of the present invention are shown. The novel use of metal stitches to reduce interconnect resistivity is shown. A series of transistors 104 are arranged in a means similar to that of FIG. 1. In this case, however, an array of transistors is used to provide an equivalent transistor of very large size. Such an arrangement would be used, for example, in a power output device. The source/drain regions of the parallel transistor stacks are labeled as A, B, and C. One set of source/drains is coupled to A by the metal line 116. The B set of source/drains is coupled to metal line 112. The C set of source/drains is coupled to metal line 108.

#As in the prior art case, the presence of the C node prevents a direct connection of A and B using the metal lines 116 and 112. A second level of metal could be used for the connection, but this may not be sufficient to keep the resistivity low enough to meet the application requirements. To overcome this problem, metal stitches, or metal wires 120, are bonded to the metal lines 116 and 112 to provide a coupling path between A and B. These metal stitches may comprise, for example, gold wire that is ultrasonically welded to the exposed metal lines 116 and 112. The metal wires 120 have an inherently much lower unit resistivity than the metal film lines 112 and 116. Further, since several wires can be bonded in parallel, the resistance between A and B can be made very low. For example, a connection having a resistance of only a few milliOhms can be constructed. Finally, if multiple metal levels exist in the integrated circuit process, multiple parallel couplings can be made using both the metal film levels and the metal stitches. In this way, the final resistivity can be kept very low. In addition, the bonding areas for the metal wires require no additional circuit area and are therefore very space efficient.