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AssigneeNEC Electronics Corporation
InventorYuichi Takada
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In a method for manufacturing a semiconductor device using a shallow trench isolation process, a silicon substrate is etched using a patterned silicon nitride layer as a mask to form a trench in the silicon substrate. Then, an insulating layer is formed in the trench and on the patterned silicon nitride layer. Then, a chemical mechanical polishing operation is performed upon the insulating layer to expose the patterned silicon nitride layer. Then, after the patterned silicon nitride layer is removed to expose the silicon is substrate, an annealing and oxidizing operation is performed upon the silicon substrate in an oxygen atmosphere or a water steam atmosphere diluted by rare gas, to grow a sacrifice silicon oxide layer on the silicon substrate.
A method for manufacturing a semiconductor device, comprising the steps of:
A method for manufacturing a semiconductor device, comprising the steps of:
Dependencies are inferred from the claim text.
No related US applications are recorded in the indexed filing history.
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Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
The components including insulated gates, e.g. IGFETs: manufacturing their isolation regions
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
Term end not estimated
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a groove-type isolation layer using a shallow trench isolation (STI) process.
2. Description of the Related Art
The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:
FIGS. 1, 2, 3, 4, 5A, 6A, 7A, 8A, 9 and 10 are cross-sectional views for explaining a prior art method for manufacturing a semiconductor device;
FIGS. 5B, 6B, 7B and 8B are cross-sectional views of partial enlargements of FIGS. 5A, 6A, 7A and 8A, respectively;
Before the description of the preferred embodiment, a prior art method for manufacturing a semiconductor device such as a MOS transistor will be explained with reference to FIGS. 1, 2, 3, 4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9 and 10. Note that FIGS. 5B, 6B, 7B and 8B are cross-sectional views of partial enlargements of FIGS. 5A, 6A, 7A and 8A, respectively.
First, referring to FIG. 1, an about 5 to 20 nm thick pad silicon oxide layer 2 and an about 100 to 300 nm thick silicon nitride layer 3 are deposited in this sequence on a monocrystalline silicon substrate 1 by a chemical vapor deposition (CVD) process. In this case, the silicon substrate 1 is of a one conductivity type such as a P-type. Then, a photoresist pattern 4 is formed on the silicon nitride layer 3 by a photolithography process to cover an active area A. Note that an area F is called a field area.
Next, referring to FIG. 2, the silicon nitride layer 3 and the pad silicon oxide layer 2 are etched by a dry etching process using the photoresist pattern 4 as a mask. Then, the photoresist pattern 4 is removed.