Integrated ram and non-volatile memory cell method and structure

#The present invention relates to semiconductor integrated circuits. More particularly, the invention provides a semiconductor memory that has integrated non-volatile and static random access memory cells. Although the invention has been applied to a single integrated circuit device in a memory application, there can be other alternatives, variations, and modifications. For example, the invention can be applied to embedded memory applications, including those with logic or micro circuits, and the like.

#Semiconductor memory devices have been widely used in electronic systems to store data. There are generally two types of memories, including a non-volatile and volatile designs. The volatile memory, such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM), loses its stored data if the power applied has been turned off. SRAMs and DRAMs often include a multitude of memory cells disposed in a two dimensional array. Due to its larger memory cell size, an SRAM is typically more expensive to manufacture than a DRAM. An SRAM typically, however, has a smaller read access time than a DRAM. Therefore, where fast access to data is needed, SRAMs are often used to store the data.

#Non-volatile semiconductor memory devices are also well known. A non-volatile semiconductor memory device, such as flash Erasable Programmable Read Only Memory (Flash EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM) or, Metal Nitride Oxide Semiconductor (MNOS), retains its charge even after the power applied thereto is turned off. Therefore, where loss of data due to power failure or termination is unacceptable, a non-volatile memory is used to store the data.

#FIG. 1 is a simplified transistor schematic diagram of a non-volatile DRAM, as known in the prior art;

#FIG. 2 is a simplified transistor schematic diagram of a non-volatile SRAM, as known in the prior art;

#FIG. 3 is a simplified transistor schematic diagram of a memory cell having both SRAM and non-volatile memory cells, in accordance with one embodiment of the present invention;

#According to the present invention, an improved memory device and method is provided. More particularly, the invention provides a semiconductor memory that has integrated non-volatile and static random access memory cells. Although the invention has been applied to a single integrated circuit device in a memory application, there can be other alternatives, variations, and modifications. For example, the invention can be applied to embedded memory applications, including those with logic or micro circuits, and the like.

#FIG. 3 is a transistor schematic diagram of memory cell 100, in accordance with one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many other variations, modifications, and alternatives. Memory cell 100 includes N-channel MNOS transistors 102, 104 which form a differential non-volatile memory cell, and N-channel Metal-Oxide-Semiconductor (MOS) transistors 106, 108, 110 and 112 which form a SRAM cell. Memory cell 100 may be part of a memory array (not shown) disposed in a semiconductor Integrated Circuit (IC) adapted, among other functions, to store and supply the stored data.

#The gate terminals of both MOS transistors 106 and 108 are coupled to input terminal W1 of memory cell 100. The drain terminals of MOS transistor 106, 108 are respectively coupled to bitlines BL and {overscore (BL)} associated with the memory cell. The source terminals of MOS transistor 106, 108 are respectively coupled to nodes C and D. The drain, gate and source terminals of MOS transistor 110 are respectively coupled to node C, node D and the Vss terminal (i.e., the ground terminal). The drain, gate and source terminals of MOS transistor 112 are respectively coupled to node D, node C and the Vss terminal.