Apparatus and method for storing and retrieving digital real time signals in their native format

#This invention relates to apparatus and method for storing and retrieving real time digital signals onto digital storage devices. More particularly, the present invention relates to apparatus and method for storing and retrieving real time digital signals in the original format of the digital signal, herein referred to as the digital signal's native format. Even more particularly, the present invention relates to apparatus and method for translating, controlling and managing digital signals using a programmable and reconfigurable embedded system.

#There are complex emerging digital products that require the storage and retrieval of digital audio and video content. The key technology driving the emergence of such new digital products is the use of local digital storage and retrieval devices, particularly the low-cost hard disk drive (HDD). The HDD allows robust, cost-effective and reliable storage of digital content with the major benefit of providing “non-linear” random access to digital content. This allows users to randomly select digital content, such as video, for playback without the burden of linear searching, such as in the case of a Video Cassette Recorder (VCR).

#Current digital products largely utilize Digital Computer architectures, typically referred to as Personal Computer (PC) architectures, employing HDD's to varying degrees for designing complex digital products, such as the Personal Video Recorder (PVR). PC architectures were originally designed as general purpose tools with rigid hardware requirements, but flexible software environments, that can accommodate sometimes very complex, demanding applications. The HDD was originally developed to support PC architectural requirements, so it is no surprise that PC architectures are usually used in digital product designs incorporating HDD's. Today, there are very few architectural design alternatives to PC architectures that can accommodate the incorporation of HDD's into digital devices for inherently complex applications, such as in the case of the PVR, without necessarily including the architectural specifications of the PC.

#For a better understanding of the present invention, reference is made to the below-referenced accompanying drawings.

#FIG. 1 is a block schematic diagram of a high level view of the method of the present invention.

#FIG. 2 is a block schematic diagram of a preferred embodiment of the invention including a detailed view of the apparatus of the present invention.

#FIG. 1 illustrates a high-level overview of the method of the present invention. An input native real-time digital signal 101 is initiated. The SSP-100 111 receives the digital signal on input and scans 1 the signal in real-time to identify its unique “signal signature” and determine the beginning of the transmitted data. The signal is then translated 2 into a format common within the present invention. The data is then forwarded to temporary memory buffers until a specific amount of data is accrued to comprise an optimal storage unit for the digital storage media 105 utilized. This storage unit is then forwarded to the digital storage media 105 and stored 3.

#On retrieval from the digital storage media 105 the digital signal data is first requested by the arbitrator 4; located on the digital media storage 105; and then forwarded to temporary memory buffers to be further manipulated by arbitration 4. Arbitration 4 can either produce specialized data handling routines such as multiple, independent digital data streams, or simply forward the requested digital signal data directly to de-translation 5. The digital signal is then de-translated 5 back to its original native format, inclusive of original timing information, for output 102.

#FIG. 2 illustrates the detailed embodiment of the present invention describing the four primary hardware subcomponents of the apparatus of the present invention: Conforming Interface 112, DMA Controller & Arbitration Block 130, Storage Interface Block 113, and Firmware Logic/Control Block 140.