US 2003/0190007 A1Published application

Jitter reduction

AssigneeFujitsu Limited

InventorsIAN JUSO DEDIC, WILLIAM GEORGE JOHN SCHOFIELD

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Abstract

Digital circuitry, for use for example in a mixed-signal device such as a digital-to-analog converter, has decoders (22, 24) which process a digital input word (D1˜Dm) to derive thermometer-coded signals (T, {overscore (T)}) for controlling one cell of an array of cells in the device. The decoders commence operation at the rising edge of a first clock signal (DIGCLK). Each cell has a first, D-type latch (26) clocked by a second clock signal (CLK2) that is delayed by a preselected delay time Δ1 relative to the first clock signal, and a second, transparent latch (32) clocked by a third clock signal (CLK3) whose rising edge coincides with the rising edge of the first clock signal and whose falling edge coincides with the rising edge of the second clock signal. The rising edge of the third clock signal is not affected by jitter associated with a delay element (28) used to delay the first clock signal by Δ1. The falling edge is affected by such jitter, so outputs (TCK, {overscore (TCK)}) of the first latch have jitter at the falling edge, but this is prevented from feeding through to final outputs (TS, {overscore (TS)}) of the circuitry because the second latch is non-transparent at that falling edge.

Claims26

Dependent claims

Digital circuitry, operative repetitively to perform a series of processing cycles, comprising:

input signal processing means operable in each cycle to perform a predetermined processing operation on one or more input signals received by the circuitry to derive therefrom one or more first signals, said predetermined processing operation being commenced in response to a first clock signal;
first clocked means switchable, by application thereto of a second clock signal, between a responsive state, in which the first clocked means are operable in response to a change in the first signal(s) to change one or more second signals produced thereby, and a non-responsive state in which no change in the second signal(s) occurs;
second clocked means switchable, by application thereto of a third clock signal, between a responsive state, in which the second clocked means are operable in response to a change in the second signal(s) to change one or more output signals of the circuitry, and a non-responsive state in which no change in the output signal(s) occurs;
and
clock generating means for deriving the second and third clock signals from the first clock signal, the second clock signal being delayed relative to the first clock signal by a preselected delay time and said third clock signal being delayed relative to the first clock signal by less than said preselected delay time such that in each cycle the first clocked means enter said non-responsive state before the end of said predetermined processing operation, and said second clocked means enter said responsive state when the first clocked means are in said non-responsive state.

2 more elements

Mixed-signal circuitry including:

digital circuitry, operative repetitively to perform a series of processing cycles, comprising:
input signal processing means operable in each cycle to perform a predetermined processing operation on one or more input signals received by the circuitry to derive therefrom one or more first signals, said predetermined processing operation being commenced in response to a first clock signal;
first clocked means switchable, by application thereto of a second clock signal, between a responsive state, in which the first clocked means are operable in response to a change in the first signal(s) to change one or more second signals produced thereby, and a non-responsive state in which no change in the second signal(s) occurs;
second clocked means switchable, by application thereto of a third clock signal, between a responsive state, in which the second clocked means are operable in response to a change in the second signal(s) to change one or more output signals of the circuitry, and a non-responsive state in which no change in the output signal(s) occurs;
and
clock generating means for deriving the second and third clock signals from the first clock signal, the second clock signal being delayed relative to the first clock signal by a preselected delay time and said third clock signal being delayed relative to the first clock signal by less than said preselected delay time such that in each cycle the first clocked means enter said non-responsive state before the end of said predetermined processing operation, and said second clocked means enter said responsive state when the first clocked means are in said non-responsive state;
and
analog circuitry connected to said digital circuitry for receiving therefrom said one or more output signals and operable to produce one or more analog signals in dependence upon the received output signal(s).

5 more elements

Dependencies are inferred from the claim text.