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US 2003/0190006 A1Published application
Data recovery circuit
OwnerHideo Naganoinventor
Life of this patent
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Abstract
A data recovery circuit includes a phase locked loop circuit that includes a phase comparator, a VCO, and a 1/N frequency divider. A sampling reference clock CLK0 multiplied in frequency with respect to an input clock CLK with a factor of 7/4 is generated. Data that corresponds to three periods of the sampling reference clock CLK0 are held in a shift register by taking four bits as the unit. On the other hand, bits output as parallel data from data in the shift register are determined based on a count in a counter that counts seven periods of the sampling reference clock CLK0.
Claims8
A data recovery circuit comprising:
- a phase locked loop unit that generates a reference clock multiplied in frequency with respect to an input clock signal, and TAP clocks that differ in phase from the reference clock, based on the input clock signal;
- an oversampling unit that conducts sampling on one bit of serial data a plurality of times by using the TAP clocks, obtains an optimum solution, and outputs the optimum solution as data of a plurality of bits in synchronism with the reference clock;
- and
- a head bit detection unit that generates a signal having a predetermined period corresponding to a plurality of periods of the clock signal and detects a head bit of the serial data from data of the plurality of bits output from the oversampling section.
1 more element
Dependencies are inferred from the claim text.