US 2003/0190004 A1 · Synchronous clock phase control circuit

Abstract

A synchronous clock phase control circuit includes a T/8 step phase clock generation unit, a phase selection unit, and four synchronous clock generation units. The T/8 step phase clock generation unit generates eight clocks previously delayed in phase by T/8 from an input clock. The phase selection unit selects four control clocks from the eight clocks generated by the phase clock generation unit based on four phase control signals, respectively. The four synchronous clock generation units synchronize the selected clocks with an externally input trigger signal TR using the input clock as a reference, and output the selected clocks when synchronization is established, respectively.

Drawings

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Drawings

Claims6

Dependent claims

A synchronous clock phase control circuit comprising:

a phase clock generation unit which generates “n” clock signals delayed by T/n×0, T/n×1, . . . and T/n×(n−1), where n>1, n is an integer and T is a cycle, from a reference clock signal and thereby having different phase delays, respectively, using an input clock signal having a cycle T input from externally as the reference clock signal;
a phase selection unit which selects “m” clock signals having different phases from the “n” clock signals having the different phases and generated by the phase clock generation unit, based on “m” control signals input from externally, respectively, where m>1 and m is an integer;
“m” clock selection units each of which selects one of the externally input clock signal and the clock signal selected by the corresponding phase selection unit, based on a corresponding detection signal;
“m” synchronous clock generation units which synchronize the clock signals selected by the clock selection units with a trigger signal asynchronous with the externally input clock signal, and output the synchronous clock signals, respectively;
and
“m” synchronous detection units which detect synchronization of the clock signals output from the synchronous clock generation units with the trigger signal, and output the corresponding detection signal to the “m” clock selection units when synchronization is detected.

3 more elements

Dependencies are inferred from the claim text.

Description3,884 words

Summary825 words

#1) Field of the Invention

#The present invention relates to a synchronous clock phase control circuit which controls a clock signal to conduct printing control in a color copier, a laser beam printer, or the like.

#2) Description of the Related Art

Brief description of the drawings5 figures

#FIG. 1 is a block diagram which shows the configuration of a synchronous clock phase control circuit in a first embodiment of this invention,

#FIG. 2 is a time chart which explains the operation of the synchronous clock phase control circuit in the first embodiment,

#FIG. 3 is a time chart which explains the operation of a T/8 step phase clock generation section shown in FIG. 1,

Detailed description2,955 words

#Embodiments of the synchronous clock phase control circuit according to the present invention will be explained hereinafter in detail with reference to the accompanying drawings.

#A first embodiment of the present invention will be explained with reference to FIG. 1 to FIG. 3. FIG. 1 is a block diagram which shows the configuration of a synchronous clock phase control circuit in the first embodiment. The synchronous clock phase control circuit in the first embodiment includes a phase selection section 10, a T/8 step phase clock generation section 20, clock selection sections 30Y, 30M, 30C and 30K, synchronous clock generation sections 40Y, 40M, 40C and 40K, and synchronous detection sections 50Y, 50M, 50C and 50K.

#The phase selection section 10 selects clocks from eight clock inputs CLK0 to CLK7 which are input from the T/8 step phase clock generation section 20, based on a Y phase control signal, an M phase control signal, a C phase control signal and a K phase control signal which are external input signals for designating the phases of clocks for Y, M, C and K, respectively. The phase selection section 10 outputs a clock CLKY selected by the Y phase control signal, a clock CLKM selected by the M phase control signal, a clock CLKC selected by the C phase control signal, and a clock CLKK selected by the K phase control signal, to the clock selection sections 30Y, 30M, 30C and 30K, respectively.

Facts

Application

10/235,957Filed 6 Sep 2002

Priority

JP 2002-1018083 Apr 2002

Published

9 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification3 codes

H03L 7/06
Automatic control of frequency or phase; Synchronisation: using a reference signal applied to a frequency- or phase-locked loop
H03L 7/0816
And where no voltage or current controlled oscillator is used: the controlled phase shifter and the frequency- or phase-detection arrangement…
H03L
Automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or

Timeline

3 Apr 2002Priority claimedJP 2002-101808
6 Sep 2002Application filedUS 10/235,957
6 Sep 2002Assigned to Mitsubishi Denki Kabushiki Kaishaassignment of assignor's interest
10 Sep 2003Assigned to Renesas Technology Corp.assignment of assignor's interest
9 Oct 2003Published
7 Apr 2004Assigned to Renesas Technology Corp.assignment of assignor's interest
15 Sep 2010Assigned to Renesas Electronics Corporationchange of name
15 Sep 2010Assigned to NEC Electronics Corporationmerger

Synchronous clock phase control circuit

Life of this patent

Synchronous clock phase control circuit

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims6

Description3,884 words

Drawings

Classification3 codes

Life of this patent

Description3,884 words