Selectable clocking architecture

#The invention generally relates to a selectable clocking architecture.

#Referring to FIG. 1, for purposes of generating an optical signal that is transmitted through an optical fiber 20, a serializer/transmitter 5 may be used. In this manner, the transmitter 5 receives bits of data in parallel from an output register 24 and converts this parallel stream of data into an output signal that indicates a serial stream of data. The output signal, in turn, is communicated to the optical fiber 20. To accomplish this, the transmitter 5 may include an input register 12 that receives in parallel bits of data (from the output register 24) to be communicated to the fiber 20. The data that is received by the input register 12 is communicated to a parallel-to-serial conversion circuit, or selector 14, that is coupled to the fiber 20 via an electrical-to-optical (E/O) converter 11. The selector 14, in turn, generates the output signal (at its output terminal) that indicates the bits of the serial stream of data. For an optical serial bus 20, the selector 14 may be coupled to the bus 20 via an optical source 11 that is driven by the output signal from the selector 14.

#Operations of the input register 12 are synchronized to edges of a clock signal (called “TXPICLK signal”) that appears on a clock signal line 19 of the transmitter 5. In this manner, in synchronization to predefined edges of the TXPICLK signal, the output register 24 receives new data and transfers stored data to the input register 12.

#FIG. 1 is a schematic diagram of a serial bus transmitter of the prior art.

#FIGS. 2 and 3 are schematic diagrams of serializers/transmitters.

#FIG. 4 is a schematic diagram of a serializer/transmitter having a selectable clocking architecture according to an embodiment of the invention.

#FIGS. 2 and 3 depict different schemes for generating clock signals that are associated with the communication of data through a transmitter or serializer to an optical fiber 51.

#More particularly, referring to FIG. 2, one such scheme involves using a serializer, or transmitter 50. The transmitter 50 includes a parallel-to-serial conversion circuit, or multiplexer 54, that furnishes a signal that indicates serial bits of data. This signal drives an electrical-to-optical (E/O) converter 21 that, in response, drives an optical signal on the optical fiber 51.

#The signal that is furnished by the multiplexer 54 indicates serial bits of data that are received in parallel by the multiplexer 54 from an input register 52 of the transmitter 50. In this manner, the input register 52 receives data from an output register 66 (of an application specific integrated circuit (ASIC) 67) and communicates data to the multiplexer 54 in synchronization with a clock signal (called “TXPICLK”) that appears on a clock signal line 70. The output register 66 receives a signal called “TXPCLK” signal (same signal as the “TXPICLK” signal apart from a phase difference due to a round trip delay mainly caused by the ASIC 67) and synchronizes the furnishing of its data to the input register 52 in synchronization with edges of the TXPICLK signal.