Clock and data recovery circuit for return-to-zero data

A phase detector for return-to-zero (RZ) data comprising:

• a first converting circuit for converting said RZ data into intermediate non-return-to-zero (NRZ) data, said first converting circuit including
• an NRZ phase detector, and
• a toggle flip-flop connected between an input line and said NRZ phase detector;
• a first sampling circuit for sampling said intermediate NRZ data to detect a phase of said intermediate NRZ data;
• and
• an exclusive-OR gate having inputs connected to two different output stages of said NRZ phase detector, said two different output stages being separated by an interim stage to provide a one clock delay between the two output stages.

A phase detector for return-to-zero (RZ) data comprising:

• a first converting circuit for converting said RZ data into intermediate non-return-to-zero (NRZ) data, said first converting circuit including
• an NRZ phase detector, and
• a toggle flip-flop connected between an input line and said NRZ phase detector;
• a first sampling circuit for sampling said intermediate NRZ data to detect a phase of said intermediate NRZ data;
• an exclusive-OR gate having inputs connected to two different output stages of said NRZ phase detector, said two different output stages being separated by an interim stage to provide a two clock delay between the two output stages;
• a slicing circuit configured to receive said dual rail signal, for providing positive and negative RZ outputs, a positive output being coupled to said first sampling circuit;
• a second converting circuit coupled to said negative output for converting RZ output data into intermediate NRZ data;
• a second sampling circuit for sampling said intermediate NRZ data to detect a phase of said NRZ data;
• a first OR-gate coupled to UP signal outputs of said first and second converting circuits;
• and
• a second OR-gate coupled to DOWN signal outputs of said first and second converting circuits.